TempleOSCDV4.05.ISO
This commit is contained in:
Terry A. Davis authored and minexew committed
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@@ -19,6 +19,8 @@ forms. Get an Intel datasheet and learn
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which forms are valid.
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{Lock|Rep}{Seg|2E=NotBr|3E=Br}{OP}{ADD}{REX}
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':' is start of alias list. Marked with OCF_ALIAS.
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*/
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R8 AL 0;
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@@ -222,7 +224,7 @@ OPCODE PUSH
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0x68, 32 !ID IMM32
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0x50,+R 16 % R16
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0x50,+R 32 R32
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0x50,+R 32 ` R64
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0x50,+R 32 `R64
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0xFF,/6 16 % RM16
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0xFF,/6 32 RM32
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0xFF,/6 32 RM64;
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@@ -238,7 +240,7 @@ OPCODE POP
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0x0F 0xA9, GS
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0x58,+R 16 R16
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0x58,+R 32 R32
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0x58,+R 32 ` R64
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0x58,+R 32 `R64
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0x8F,/0 16 RM16
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0x8F,/0 32 RM32
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0x8F,/0 32 RM64;
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@@ -269,7 +271,7 @@ OPCODE MOV
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0xB8,+R 16 R16 IMM16
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0xB8,+R 32 &R32 UIMM32
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0xB8,+R 32 R32 IMM32
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0xB8,+R 32 ` R64 UIMM32
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0xB8,+R 32 `R64 UIMM32
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0xB8,+R 32 &R64 UIMM64
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0xB8,+R 32 R64 IMM64
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0xC6, &RM8 UIMM8
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@@ -278,7 +280,7 @@ OPCODE MOV
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0xC7, 16 RM16 IMM16
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0xC7, 32 &RM32 UIMM32
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0xC7, 32 RM32 IMM32
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0xC7, 32 ` RM64 UIMM32
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0xC7, 32 `RM64 UIMM32
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0xC7, 32 RM64 IMM32;
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OPCODE ADC
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@@ -498,133 +500,77 @@ OPCODE XOR
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0x31,/R 32 RM32 R32
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0x31,/R 32 ^ RM64 R64;
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OPCODE CMOVA
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0x0F 0x47,/R 16 R16 RM16
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0x0F 0x47,/R 32 R32 RM32
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0x0F 0x47,/R 32 R64 RM64;
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OPCODE CMOVAE
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0x0F 0x43,/R 16 R16 RM16
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0x0F 0x43,/R 32 R32 RM32
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0x0F 0x43,/R 32 R64 RM64;
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OPCODE CMOVB
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0x0F 0x42,/R 16 R16 RM16
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0x0F 0x42,/R 32 R32 RM32
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0x0F 0x42,/R 32 R64 RM64;
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OPCODE CMOVBE
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0x0F 0x46,/R 16 R16 RM16
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0x0F 0x46,/R 32 R32 RM32
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0x0F 0x46,/R 32 R64 RM64;
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OPCODE CMOVC
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0x0F 0x42,/R 16 R16 RM16
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0x0F 0x42,/R 32 R32 RM32
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0x0F 0x42,/R 32 R64 RM64;
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OPCODE CMOVE
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0x0F 0x44,/R 16 R16 RM16
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0x0F 0x44,/R 32 R32 RM32
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0x0F 0x44,/R 32 R64 RM64;
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OPCODE CMOVG
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0x0F 0x4F,/R 16 R16 RM16
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0x0F 0x4F,/R 32 R32 RM32
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0x0F 0x4F,/R 32 R64 RM64;
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OPCODE CMOVGE
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0x0F 0x4D,/R 16 R16 RM16
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0x0F 0x4D,/R 32 R32 RM32
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0x0F 0x4D,/R 32 R64 RM64;
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OPCODE CMOVL
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0x0F 0x4C,/R 16 R16 RM16
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0x0F 0x4C,/R 32 R32 RM32
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0x0F 0x4C,/R 32 R64 RM64;
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OPCODE CMOVLE
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0x0F 0x4E,/R 16 R16 RM16
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0x0F 0x4E,/R 32 R32 RM32
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0x0F 0x4E,/R 32 R64 RM64;
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OPCODE CMOVNA
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0x0F 0x46,/R 16 R16 RM16
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0x0F 0x46,/R 32 R32 RM32
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0x0F 0x46,/R 32 R64 RM64;
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OPCODE CMOVNAE
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0x0F 0x42,/R 16 R16 RM16
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0x0F 0x42,/R 32 R32 RM32
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0x0F 0x42,/R 32 R64 RM64;
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OPCODE CMOVNB
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0x0F 0x43,/R 16 R16 RM16
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0x0F 0x43,/R 32 R32 RM32
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0x0F 0x43,/R 32 R64 RM64;
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OPCODE CMOVNBE
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0x0F 0x47,/R 16 R16 RM16
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0x0F 0x47,/R 32 R32 RM32
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0x0F 0x47,/R 32 R64 RM64;
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OPCODE CMOVNC
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0x0F 0x43,/R 16 R16 RM16
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0x0F 0x43,/R 32 R32 RM32
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0x0F 0x43,/R 32 R64 RM64;
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OPCODE CMOVNE
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0x0F 0x45,/R 16 R16 RM16
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0x0F 0x45,/R 32 R32 RM32
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0x0F 0x45,/R 32 R64 RM64;
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OPCODE CMOVNG
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0x0F 0x4E,/R 16 R16 RM16
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0x0F 0x4E,/R 32 R32 RM32
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0x0F 0x4E,/R 32 R64 RM64;
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OPCODE CMOVNGE
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0x0F 0x4C,/R 16 R16 RM16
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0x0F 0x4C,/R 32 R32 RM32
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0x0F 0x4C,/R 32 R64 RM64;
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OPCODE CMOVNL
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0x0F 0x4D,/R 16 R16 RM16
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0x0F 0x4D,/R 32 R32 RM32
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0x0F 0x4D,/R 32 R64 RM64;
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OPCODE CMOVNLE
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0x0F 0x4F,/R 16 R16 RM16
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0x0F 0x4F,/R 32 R32 RM32
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0x0F 0x4F,/R 32 R64 RM64;
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OPCODE CMOVNO
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0x0F 0x41,/R 16 R16 RM16
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0x0F 0x41,/R 32 R32 RM32
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0x0F 0x41,/R 32 R64 RM64;
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OPCODE CMOVNP
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0x0F 0x4B,/R 16 R16 RM16
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0x0F 0x4B,/R 32 R32 RM32
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0x0F 0x4B,/R 32 R64 RM64;
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OPCODE CMOVNS
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0x0F 0x49,/R 16 R16 RM16
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0x0F 0x49,/R 32 R32 RM32
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0x0F 0x49,/R 32 R64 RM64;
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OPCODE CMOVNZ
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0x0F 0x45,/R 16 R16 RM16
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0x0F 0x45,/R 32 R32 RM32
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0x0F 0x45,/R 32 R64 RM64;
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OPCODE CMOVO
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0x0F 0x40,/R 16 R16 RM16
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0x0F 0x40,/R 32 R32 RM32
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0x0F 0x40,/R 32 R64 RM64;
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OPCODE CMOVP
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0x0F 0x4A,/R 16 R16 RM16
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0x0F 0x4A,/R 32 R32 RM32
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0x0F 0x4A,/R 32 R64 RM64;
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OPCODE CMOVPE
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0x0F 0x4A,/R 16 R16 RM16
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0x0F 0x4A,/R 32 R32 RM32
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0x0F 0x4A,/R 32 R64 RM64;
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OPCODE CMOVPO
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0x0F 0x4B,/R 16 R16 RM16
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0x0F 0x4B,/R 32 R32 RM32
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0x0F 0x4B,/R 32 R64 RM64;
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OPCODE CMOVNO
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0x0F 0x41,/R 16 R16 RM16
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0x0F 0x41,/R 32 R32 RM32
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0x0F 0x41,/R 32 R64 RM64;
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OPCODE CMOVB
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0x0F 0x42,/R 16 R16 RM16
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0x0F 0x42,/R 32 R32 RM32
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0x0F 0x42,/R 32 R64 RM64 :CMOVC CMOVNAE;
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OPCODE CMOVAE
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0x0F 0x43,/R 16 R16 RM16
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0x0F 0x43,/R 32 R32 RM32
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0x0F 0x43,/R 32 R64 RM64 :CMOVNB CMOVNC;
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OPCODE CMOVE
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0x0F 0x44,/R 16 R16 RM16
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0x0F 0x44,/R 32 R32 RM32
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0x0F 0x44,/R 32 R64 RM64 :CMOVZ;
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OPCODE CMOVNE
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0x0F 0x45,/R 16 R16 RM16
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0x0F 0x45,/R 32 R32 RM32
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0x0F 0x45,/R 32 R64 RM64 :CMOVNZ;
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OPCODE CMOVBE
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0x0F 0x46,/R 16 R16 RM16
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0x0F 0x46,/R 32 R32 RM32
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0x0F 0x46,/R 32 R64 RM64 :CMOVNA;
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OPCODE CMOVA
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0x0F 0x47,/R 16 R16 RM16
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0x0F 0x47,/R 32 R32 RM32
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0x0F 0x47,/R 32 R64 RM64 :CMOVNBE;
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OPCODE CMOVS
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0x0F 0x48,/R 16 R16 RM16
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0x0F 0x48,/R 32 R32 RM32
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0x0F 0x48,/R 32 R64 RM64;
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OPCODE CMOVZ
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0x0F 0x44,/R 16 R16 RM16
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0x0F 0x44,/R 32 R32 RM32
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0x0F 0x44,/R 32 R64 RM64;
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OPCODE CMOVNS
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0x0F 0x49,/R 16 R16 RM16
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0x0F 0x49,/R 32 R32 RM32
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0x0F 0x49,/R 32 R64 RM64;
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OPCODE CMOVP
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0x0F 0x4A,/R 16 R16 RM16
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0x0F 0x4A,/R 32 R32 RM32
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0x0F 0x4A,/R 32 R64 RM64 :CMOVPE;
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OPCODE CMOVNP
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0x0F 0x4B,/R 16 R16 RM16
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0x0F 0x4B,/R 32 R32 RM32
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0x0F 0x4B,/R 32 R64 RM64 :CMOVPO;
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OPCODE CMOVL
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0x0F 0x4C,/R 16 R16 RM16
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0x0F 0x4C,/R 32 R32 RM32
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0x0F 0x4C,/R 32 R64 RM64 :CMOVNGE;
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OPCODE CMOVGE
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0x0F 0x4D,/R 16 R16 RM16
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0x0F 0x4D,/R 32 R32 RM32
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0x0F 0x4D,/R 32 R64 RM64 :CMOVNL;
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OPCODE CMOVLE
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0x0F 0x4E,/R 16 R16 RM16
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0x0F 0x4E,/R 32 R32 RM32
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0x0F 0x4E,/R 32 R64 RM64 :CMOVNG;
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OPCODE CMOVG
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0x0F 0x4F,/R 16 R16 RM16
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0x0F 0x4F,/R 32 R32 RM32
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0x0F 0x4F,/R 32 R64 RM64 :CMOVNLE;
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OPCODE CALL
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0xE8, 16 !&CW REL16
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0xFF,/2 16 ! RM16
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0xE8, 32 !&CD REL32
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0xFF,/2 32 ! RM32
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0xFF,/2 32 !` RM64
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0xFF,/2 32 !`RM64
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// 0x9A, CD PTR1616
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// 0xFF,/3 16 M1616
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// 0x9A, 16 CP PTR1632
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@@ -639,132 +585,74 @@ OPCODE JMP
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0xFF,/4 16 ! RM16
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0xFF,/4 32 ! RM32
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0xFF,/4 32 ! RM64;
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OPCODE JA
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0x77, &CB REL8
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0x0F 0x87, 16 !CW REL16
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0x0F 0x87, 32 !CD REL32;
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OPCODE JAE
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0x73, &CB REL8
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0x0F 0x83, 16 !CW REL16
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0x0F 0x83, 32 !CD REL32;
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OPCODE JB
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0x72, &CB REL8
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0x0F 0x82, 16 !CW REL16
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0x0F 0x82, 32 !CD REL32;
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OPCODE JBE
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0x76, &CB REL8
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0x0F 0x86, 16 !CW REL16
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0x0F 0x86, 32 !CD REL32;
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OPCODE JC
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0x72, &CB REL8
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0x0F 0x82, 16 !CW REL16
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0x0F 0x82, 32 !CD REL32;
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OPCODE JCXZ
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0xE3, CB REL8;
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OPCODE JECXZ
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0xE3, CB REL8;
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OPCODE JRCXZ
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0xE3, CB REL8;
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OPCODE JE
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0x74, &CB REL8
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0x0F 0x84, 16 !CW REL16
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0x0F 0x84, 32 !CD REL32;
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OPCODE JG
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0x7F, &CB REL8
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0x0F 0x8F, 16 !CW REL16
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0x0F 0x8F, 32 !CD REL32;
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OPCODE JGE
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0x7D, &CB REL8
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0x0F 0x8D, 16 !CW REL16
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0x0F 0x8D, 32 !CD REL32;
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OPCODE JL
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0x7C, &CB REL8
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0x0F 0x8C, 16 !CW REL16
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0x0F 0x8C, 32 !CD REL32;
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OPCODE JLE
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0x7E, &CB REL8
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0x0F 0x8E, 16 !CW REL16
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0x0F 0x8E, 32 !CD REL32;
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OPCODE JNA
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0x76, &CB REL8
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0x0F 0x86, 16 !CW REL16
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0x0F 0x86, 32 !CD REL32;
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OPCODE JNAE
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0x72, &CB REL8
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0x0F 0x82, 16 !CW REL16
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0x0F 0x82, 32 !CD REL32;
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OPCODE JNB
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0x73, &CB REL8
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0x0F 0x83, 16 !CW REL16
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0x0F 0x83, 32 !CD REL32;
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OPCODE JNBE
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0x77, &CB REL8
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0x0F 0x87, 16 !CW REL16
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0x0F 0x87, 32 !CD REL32;
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OPCODE JNC
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0x73, &CB REL8
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0x0F 0x83, 16 !CW REL16
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0x0F 0x83, 32 !CD REL32;
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OPCODE JNE
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0x75, &CB REL8
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0x0F 0x85, 16 !CW REL16
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0x0F 0x85, 32 !CD REL32;
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OPCODE JNG
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0x7E, &CB REL8
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0x0F 0x8E, 16 !CW REL16
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0x0F 0x8E, 32 !CD REL32;
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OPCODE JNGE
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0x7C, &CB REL8
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0x0F 0x8C, 16 !CW REL16
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0x0F 0x8C, 32 !CD REL32;
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OPCODE JNL
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0x7D, &CB REL8
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0x0F 0x8D, 16 !CW REL16
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0x0F 0x8D, 32 !CD REL32;
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OPCODE JNLE
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0x7F, &CB REL8
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0x0F 0x8F, 16 !CW REL16
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0x0F 0x8F, 32 !CD REL32;
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OPCODE JNO
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0x71, &CB REL8
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0x0F 0x81, 16 !CW REL16
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0x0F 0x81, 32 !CD REL32;
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OPCODE JNP
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0x7B, &CB REL8
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0x0F 0x8B, 16 !CW REL16
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0x0F 0x8B, 32 !CD REL32;
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OPCODE JNS
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0x79, &CB REL8
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0x0F 0x89, 16 !CW REL16
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0x0F 0x89, 32 !CD REL32;
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OPCODE JNZ
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0x75, &CB REL8
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0x0F 0x85, 16 !CW REL16
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0x0F 0x85, 32 !CD REL32;
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OPCODE JO
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0x70, &CB REL8
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0x0F 0x80, 16 !CW REL16
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0x0F 0x80, 32 !CD REL32;
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OPCODE JP
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0x7A, &CB REL8
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0x0F 0x8A, 16 !CW REL16
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0x0F 0x8A, 32 !CD REL32;
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OPCODE JPE
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0x7A, &CB REL8
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0x0F 0x8A, 16 !CW REL16
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0x0F 0x8A, 32 !CD REL32;
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OPCODE JPO
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0x7B, &CB REL8
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0x0F 0x8B, 16 !CW REL16
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0x0F 0x8B, 32 !CD REL32;
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OPCODE JNO
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0x71, &CB REL8
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0x0F 0x81, 16 !CW REL16
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0x0F 0x81, 32 !CD REL32;
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OPCODE JB
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0x72, &CB REL8
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0x0F 0x82, 16 !CW REL16
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0x0F 0x82, 32 !CD REL32 :JC JNAE;
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OPCODE JAE
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0x73, &CB REL8
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0x0F 0x83, 16 !CW REL16
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0x0F 0x83, 32 !CD REL32 :JNB JNC;
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OPCODE JE
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0x74, &CB REL8
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0x0F 0x84, 16 !CW REL16
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0x0F 0x84, 32 !CD REL32 :JZ;
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OPCODE JNE
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0x75, &CB REL8
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0x0F 0x85, 16 !CW REL16
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0x0F 0x85, 32 !CD REL32 :JNZ;
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OPCODE JBE
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0x76, &CB REL8
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0x0F 0x86, 16 !CW REL16
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0x0F 0x86, 32 !CD REL32 :JNA;
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OPCODE JA
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0x77, &CB REL8
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0x0F 0x87, 16 !CW REL16
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0x0F 0x87, 32 !CD REL32 :JNBE;
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OPCODE JS
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0x78, &CB REL8
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0x0F 0x88, 16 !CW REL16
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0x0F 0x88, 32 !CD REL32;
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OPCODE JZ
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0x74, &CB REL8
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0x0F 0x84, 16 !CW REL16
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0x0F 0x84, 32 !CD REL32;
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OPCODE JNS
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0x79, &CB REL8
|
||||
0x0F 0x89, 16 !CW REL16
|
||||
0x0F 0x89, 32 !CD REL32;
|
||||
OPCODE JP
|
||||
0x7A, &CB REL8
|
||||
0x0F 0x8A, 16 !CW REL16
|
||||
0x0F 0x8A, 32 !CD REL32 :JPE;
|
||||
OPCODE JNP
|
||||
0x7B, &CB REL8
|
||||
0x0F 0x8B, 16 !CW REL16
|
||||
0x0F 0x8B, 32 !CD REL32 :JPO;
|
||||
OPCODE JL
|
||||
0x7C, &CB REL8
|
||||
0x0F 0x8C, 16 !CW REL16
|
||||
0x0F 0x8C, 32 !CD REL32 :JNGE;
|
||||
OPCODE JGE
|
||||
0x7D, &CB REL8
|
||||
0x0F 0x8D, 16 !CW REL16
|
||||
0x0F 0x8D, 32 !CD REL32 :JNL;
|
||||
OPCODE JLE
|
||||
0x7E, &CB REL8
|
||||
0x0F 0x8E, 16 !CW REL16
|
||||
0x0F 0x8E, 32 !CD REL32 :JNG;
|
||||
OPCODE JG
|
||||
0x7F, &CB REL8
|
||||
0x0F 0x8F, 16 !CW REL16
|
||||
0x0F 0x8F, 32 !CD REL32 :JNLE;
|
||||
|
||||
OPCODE JCXZ
|
||||
0xE3, CB REL8 :JECXZ JRCXZ;
|
||||
|
||||
OPCODE INC
|
||||
0x40,+R 16 % R16
|
||||
@@ -979,10 +867,8 @@ OPCODE LODSW 0xAD, 16;
|
||||
OPCODE LODSD 0xAD, 32;
|
||||
OPCODE LODSQ 0xAD, 32=;
|
||||
OPCODE LOOP 0xE2, CB REL8;
|
||||
OPCODE LOOPE 0xE1, CB REL8;
|
||||
OPCODE LOOPZ 0xE1, CB REL8;
|
||||
OPCODE LOOPNE 0xE0, CB REL8;
|
||||
OPCODE LOOPNZ 0xE0, CB REL8;
|
||||
OPCODE LOOPE 0xE1, CB REL8 :LOOPZ;
|
||||
OPCODE LOOPNE 0xE0, CB REL8 :LOOPNZ;
|
||||
OPCODE LSL
|
||||
0x0F 0x03,/R 16 R16 RM16
|
||||
0x0F 0x03,/R 32 R32 RM32
|
||||
@@ -1072,36 +958,22 @@ OPCODE SEGDS 0x3E;
|
||||
OPCODE SEGES 0x26;
|
||||
OPCODE SEGFS 0x64;
|
||||
OPCODE SEGGS 0x65;
|
||||
OPCODE SETA 0x0F 0x97, RM8;
|
||||
OPCODE SETAE 0x0F 0x93, RM8;
|
||||
OPCODE SETB 0x0F 0x92, RM8;
|
||||
OPCODE SETBE 0x0F 0x96, RM8;
|
||||
OPCODE SETC 0x0F 0x92, RM8;
|
||||
OPCODE SETE 0x0F 0x94, RM8;
|
||||
OPCODE SETG 0x0F 0x9F, RM8;
|
||||
OPCODE SETGE 0x0F 0x9D, RM8;
|
||||
OPCODE SETL 0x0F 0x9C, RM8;
|
||||
OPCODE SETLE 0x0F 0x9E, RM8;
|
||||
OPCODE SETNA 0x0F 0x96, RM8;
|
||||
OPCODE SETNAE 0x0F 0x92, RM8;
|
||||
OPCODE SETNB 0x0F 0x93, RM8;
|
||||
OPCODE SETNBE 0x0F 0x97, RM8;
|
||||
OPCODE SETNC 0x0F 0x93, RM8;
|
||||
OPCODE SETNE 0x0F 0x95, RM8;
|
||||
OPCODE SETNG 0x0F 0x9E, RM8;
|
||||
OPCODE SETNGE 0x0F 0x9C, RM8;
|
||||
OPCODE SETNL 0x0F 0x9D, RM8;
|
||||
OPCODE SETNLE 0x0F 0x9F, RM8;
|
||||
OPCODE SETO 0x0F 0x90, RM8;
|
||||
OPCODE SETNO 0x0F 0x91, RM8;
|
||||
OPCODE SETNP 0x0F 0x9B, RM8;
|
||||
OPCODE SETB 0x0F 0x92, RM8 :SETC SETNAE;
|
||||
OPCODE SETAE 0x0F 0x93, RM8 :SETNC SETNB;
|
||||
OPCODE SETE 0x0F 0x94, RM8 :SETZ;
|
||||
OPCODE SETNE 0x0F 0x95, RM8 :SETNZ;
|
||||
OPCODE SETBE 0x0F 0x96, RM8 :SETNA;
|
||||
OPCODE SETA 0x0F 0x97, RM8 :SETNBE;
|
||||
OPCODE SETS 0x0F 0x98, RM8;
|
||||
OPCODE SETNS 0x0F 0x99, RM8;
|
||||
OPCODE SETNZ 0x0F 0x95, RM8;
|
||||
OPCODE SETO 0x0F 0x90, RM8;
|
||||
OPCODE SETP 0x0F 0x9A, RM8;
|
||||
OPCODE SETPE 0x0F 0x9A, RM8;
|
||||
OPCODE SETPO 0x0F 0x9B, RM8;
|
||||
OPCODE SETS 0x0F 0x98, RM8;
|
||||
OPCODE SETZ 0x0F 0x94, RM8;
|
||||
OPCODE SETP 0x0F 0x9A, RM8 :SETPE;
|
||||
OPCODE SETNP 0x0F 0x9B, RM8 :SETPO;
|
||||
OPCODE SETL 0x0F 0x9C, RM8 :SETNGE;
|
||||
OPCODE SETGE 0x0F 0x9D, RM8 :SETNL;
|
||||
OPCODE SETLE 0x0F 0x9E, RM8 :SETNG;
|
||||
OPCODE SETG 0x0F 0x9F, RM8 :SETNLE;
|
||||
OPCODE SHLD
|
||||
0x0F 0xA5,/R 16 RM16 R16
|
||||
0x0F 0xA5,/R 32 RM32 R32
|
||||
@@ -1138,42 +1010,6 @@ OPCODE XADD
|
||||
0x0F 0xC1,/R 32 RM64 R64;
|
||||
OPCODE XLATB 0xD7;
|
||||
|
||||
OPCODE RCL
|
||||
0xD2,/2 RM8 CL
|
||||
0xD3,/2 16 RM16 CL
|
||||
0xD3,/2 32 RM32 CL
|
||||
0xD3,/2 32 RM64 CL
|
||||
0xC0,/2 IB &RM8 UIMM8
|
||||
0xC0,/2 IB RM8 IMM8
|
||||
0xC1,/2 16 IB &RM16 UIMM8
|
||||
0xC1,/2 16 IB RM16 IMM8
|
||||
0xC1,/2 32 IB &RM32 UIMM8
|
||||
0xC1,/2 32 IB RM32 IMM8
|
||||
0xC1,/2 32 IB &RM64 UIMM8
|
||||
0xC1,/2 32 IB RM64 IMM8;
|
||||
OPCODE RCL1
|
||||
0xD0,/2 RM8
|
||||
0xD1,/2 16 RM16
|
||||
0xD1,/2 32 RM32
|
||||
0xD1,/2 32 RM64;
|
||||
OPCODE RCR
|
||||
0xD2,/3 RM8 CL
|
||||
0xD3,/3 16 RM16 CL
|
||||
0xD3,/3 32 RM32 CL
|
||||
0xD3,/3 32 RM64 CL
|
||||
0xC0,/3 IB &RM8 UIMM8
|
||||
0xC0,/3 IB RM8 IMM8
|
||||
0xC1,/3 16 IB &RM16 UIMM8
|
||||
0xC1,/3 16 IB RM16 IMM8
|
||||
0xC1,/3 32 IB &RM32 UIMM8
|
||||
0xC1,/3 32 IB RM32 IMM8
|
||||
0xC1,/3 32 IB &RM64 UIMM8
|
||||
0xC1,/3 32 IB RM64 IMM8;
|
||||
OPCODE RCR1
|
||||
0xD0,/3 RM8
|
||||
0xD1,/3 16 RM16
|
||||
0xD1,/3 32 RM32
|
||||
0xD1,/3 32 RM64;
|
||||
OPCODE ROL
|
||||
0xD2,/0 RM8 CL
|
||||
0xD3,/0 16 RM16 CL
|
||||
@@ -1210,8 +1046,43 @@ OPCODE ROR1
|
||||
0xD1,/1 16 RM16
|
||||
0xD1,/1 32 RM32
|
||||
0xD1,/1 32 RM64;
|
||||
|
||||
OPCODE SAL
|
||||
OPCODE RCL
|
||||
0xD2,/2 RM8 CL
|
||||
0xD3,/2 16 RM16 CL
|
||||
0xD3,/2 32 RM32 CL
|
||||
0xD3,/2 32 RM64 CL
|
||||
0xC0,/2 IB &RM8 UIMM8
|
||||
0xC0,/2 IB RM8 IMM8
|
||||
0xC1,/2 16 IB &RM16 UIMM8
|
||||
0xC1,/2 16 IB RM16 IMM8
|
||||
0xC1,/2 32 IB &RM32 UIMM8
|
||||
0xC1,/2 32 IB RM32 IMM8
|
||||
0xC1,/2 32 IB &RM64 UIMM8
|
||||
0xC1,/2 32 IB RM64 IMM8;
|
||||
OPCODE RCL1
|
||||
0xD0,/2 RM8
|
||||
0xD1,/2 16 RM16
|
||||
0xD1,/2 32 RM32
|
||||
0xD1,/2 32 RM64;
|
||||
OPCODE RCR
|
||||
0xD2,/3 RM8 CL
|
||||
0xD3,/3 16 RM16 CL
|
||||
0xD3,/3 32 RM32 CL
|
||||
0xD3,/3 32 RM64 CL
|
||||
0xC0,/3 IB &RM8 UIMM8
|
||||
0xC0,/3 IB RM8 IMM8
|
||||
0xC1,/3 16 IB &RM16 UIMM8
|
||||
0xC1,/3 16 IB RM16 IMM8
|
||||
0xC1,/3 32 IB &RM32 UIMM8
|
||||
0xC1,/3 32 IB RM32 IMM8
|
||||
0xC1,/3 32 IB &RM64 UIMM8
|
||||
0xC1,/3 32 IB RM64 IMM8;
|
||||
OPCODE RCR1
|
||||
0xD0,/3 RM8
|
||||
0xD1,/3 16 RM16
|
||||
0xD1,/3 32 RM32
|
||||
0xD1,/3 32 RM64;
|
||||
OPCODE SHL
|
||||
0xD2,/4 RM8 CL
|
||||
0xD3,/4 16 RM16 CL
|
||||
0xD3,/4 32 RM32 CL
|
||||
@@ -1223,13 +1094,30 @@ OPCODE SAL
|
||||
0xC1,/4 32 IB &RM32 UIMM8
|
||||
0xC1,/4 32 IB RM32 IMM8
|
||||
0xC1,/4 32 IB &RM64 UIMM8
|
||||
0xC1,/4 32 IB RM64 IMM8;
|
||||
OPCODE SAL1
|
||||
0xC1,/4 32 IB RM64 IMM8 :SAL;
|
||||
OPCODE SHL1
|
||||
0xD0,/4 RM8
|
||||
0xD1,/4 16 RM16
|
||||
0xD1,/4 32 RM32
|
||||
0xD1,/4 32 RM64;
|
||||
|
||||
0xD1,/4 32 RM64 :SAL1;
|
||||
OPCODE SHR
|
||||
0xD2,/5 RM8 CL
|
||||
0xD3,/5 16 RM16 CL
|
||||
0xD3,/5 32 RM32 CL
|
||||
0xD3,/5 32 RM64 CL
|
||||
0xC0,/5 IB &RM8 UIMM8
|
||||
0xC0,/5 IB RM8 IMM8
|
||||
0xC1,/5 16 IB &RM16 UIMM8
|
||||
0xC1,/5 16 IB RM16 IMM8
|
||||
0xC1,/5 32 IB &RM32 UIMM8
|
||||
0xC1,/5 32 IB RM32 IMM8
|
||||
0xC1,/5 32 IB &RM64 UIMM8
|
||||
0xC1,/5 32 IB RM64 IMM8;
|
||||
OPCODE SHR1
|
||||
0xD0,/5 RM8
|
||||
0xD1,/5 16 RM16
|
||||
0xD1,/5 32 RM32
|
||||
0xD1,/5 32 RM64;
|
||||
OPCODE SAR
|
||||
0xD2,/7 RM8 CL
|
||||
0xD3,/7 16 RM16 CL
|
||||
@@ -1249,63 +1137,25 @@ OPCODE SAR1
|
||||
0xD1,/7 32 RM32
|
||||
0xD1,/7 32 RM64;
|
||||
|
||||
OPCODE SHL
|
||||
0xD2,/4 RM8 CL
|
||||
0xD3,/4 16 RM16 CL
|
||||
0xD3,/4 32 RM32 CL
|
||||
0xD3,/4 32 RM64 CL
|
||||
0xC0,/4 IB &RM8 UIMM8
|
||||
0xC0,/4 IB RM8 IMM8
|
||||
0xC1,/4 16 IB &RM16 UIMM8
|
||||
0xC1,/4 16 IB RM16 IMM8
|
||||
0xC1,/4 32 IB &RM32 UIMM8
|
||||
0xC1,/4 32 IB RM32 IMM8
|
||||
0xC1,/4 32 IB &RM64 UIMM8
|
||||
0xC1,/4 32 IB RM64 IMM8;
|
||||
OPCODE SHL1
|
||||
0xD0,/4 RM8
|
||||
0xD1,/4 16 RM16
|
||||
0xD1,/4 32 RM32
|
||||
0xD1,/4 32 RM64;
|
||||
|
||||
OPCODE SHR
|
||||
0xD2,/5 RM8 CL
|
||||
0xD3,/5 16 RM16 CL
|
||||
0xD3,/5 32 RM32 CL
|
||||
0xD3,/5 32 RM64 CL
|
||||
0xC0,/5 IB &RM8 UIMM8
|
||||
0xC0,/5 IB RM8 IMM8
|
||||
0xC1,/5 16 IB &RM16 UIMM8
|
||||
0xC1,/5 16 IB RM16 IMM8
|
||||
0xC1,/5 32 IB &RM32 UIMM8
|
||||
0xC1,/5 32 IB RM32 IMM8
|
||||
0xC1,/5 32 IB &RM64 UIMM8
|
||||
0xC1,/5 32 IB RM64 IMM8;
|
||||
OPCODE SHR1
|
||||
0xD0,/5 RM8
|
||||
0xD1,/5 16 RM16
|
||||
0xD1,/5 32 RM32
|
||||
0xD1,/5 32 RM64;
|
||||
|
||||
OPCODE FILD
|
||||
0xDF,/0 M16 //Load I16
|
||||
0xDB,/0 M32 //Load I32
|
||||
0xDF,/5 ` M64; //Load I64
|
||||
0xDF,/5 `M64; //Load I64
|
||||
OPCODE FISTP
|
||||
0xDF,/7 ` M64; //Store I64
|
||||
0xDF,/7 `M64; //Store I64
|
||||
OPCODE FISTTP
|
||||
0xDD,/1 ` M64; //Store I64
|
||||
0xDD,/1 `M64; //Store I64
|
||||
OPCODE FLD
|
||||
0xD9,/0 M32 //Load F32
|
||||
0xDD,/0 ` M64 //Load F64
|
||||
0xDD,/0 `M64 //Load F64
|
||||
0xD9 0xC0,+I* STI;
|
||||
OPCODE FSTP
|
||||
0xD9,/3 M32 //Store F32
|
||||
0xDD,/3 ` M64 //Store F64
|
||||
0xDD,/3 `M64 //Store F64
|
||||
0xDD 0xD8,+I* STI;
|
||||
OPCODE FST
|
||||
0xD9,/2 M32 //Store F32
|
||||
0xDD,/2 ` M64 //Store F64
|
||||
0xDD,/2 `M64 //Store F64
|
||||
0xDD 0xD0,+I* STI;
|
||||
OPCODE FRSTOR
|
||||
0xDD,/4 M32
|
||||
@@ -1327,7 +1177,7 @@ OPCODE FSQRT 0xD9 0xFA,*;
|
||||
OPCODE FMULP 0xDE 0xC8,+I* STI ST0;
|
||||
OPCODE FMUL
|
||||
0xD8,/1 ST0 M32
|
||||
0xDC,/1 ` ST0 M64
|
||||
0xDC,/1 `ST0 M64
|
||||
0xD8 0xC8,+I* ST0 STI
|
||||
0xDC 0xC8,+I* STI ST0;
|
||||
OPCODE FIMUL
|
||||
@@ -1336,32 +1186,32 @@ OPCODE FIMUL
|
||||
OPCODE FDIVP 0xDE 0xF8,+I* STI ST0;
|
||||
OPCODE FDIV
|
||||
0xD8,/6 ST0 M32
|
||||
0xDC,/6 ` ST0 M64
|
||||
0xDC,/6 `ST0 M64
|
||||
0xD8 0xF0,+I* ST0 STI
|
||||
0xDC 0xF8,+I* STI ST0;
|
||||
OPCODE FDIVRP 0xDE 0xF0,+I* STI ST0;
|
||||
OPCODE FDIVR
|
||||
0xD8,/7 ST0 M32
|
||||
0xDC,/7 ` ST0 M64
|
||||
0xDC,/7 `ST0 M64
|
||||
0xD8 0xF8,+I* ST0 STI
|
||||
0xDC 0xF0,+I* STI ST0;
|
||||
OPCODE FPREM 0xD9 0xF8,*;
|
||||
OPCODE FADDP 0xDE 0xC0,+I* STI ST0;
|
||||
OPCODE FADD
|
||||
0xD8,/0 ST0 M32
|
||||
0xDC,/0 ` ST0 M64
|
||||
0xDC,/0 `ST0 M64
|
||||
0xD8 0xC0,+I* ST0 STI
|
||||
0xDC 0xC0,+I* STI ST0;
|
||||
OPCODE FSUBP 0xDE 0xE8,+I* STI ST0;
|
||||
OPCODE FSUB
|
||||
0xD8,/4 ST0 M32
|
||||
0xDC,/4 ` ST0 M64
|
||||
0xDC,/4 `ST0 M64
|
||||
0xD8 0xE0,+I* ST0 STI
|
||||
0xDC 0xE8,+I* STI ST0;
|
||||
OPCODE FSUBRP 0xDE 0xE0,+I* STI ST0;
|
||||
OPCODE FSUBR
|
||||
0xD8,/5 ST0 M32
|
||||
0xDC,/5 ` ST0 M64
|
||||
0xDC,/5 `ST0 M64
|
||||
0xD8 0xE8,+I* ST0 STI
|
||||
0xDC 0xE0,+I* STI ST0;
|
||||
OPCODE FCOMIP 0xDF 0xF0,+I* ST0 STI;
|
||||
|
||||
Reference in new issue
Block a user