Initial (manual) import
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@@ -0,0 +1,89 @@
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$WW,1$$FG,5$$TX+CX,"64-Bit Assembly Quiz"$$FG$
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1) In 64-bit mode, how many bytes are always pushed?
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PUSH 12
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PUSH EAX
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2) What happens to the upper 32-bits?
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XOR EAX,EAX
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MOV EAX,0x12345678
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MOV EAX,0x80000000
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3) How do you set FS or GS values?
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4) If FS points to current task record, what's wrong with this instruction?
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MOV RAX,U64 FS:[TSS_SOME_MEMBER]
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5) Which instruction takes more bytes?
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MOV RAX,U64 [R8]
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MOV RAX,U64 [R13]
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6) Are these the same number of bytes?
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MOV RAX,1234
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MOV R8,1234
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MOV EAX,1234
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7) True or False
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a) You can access the lowest byte of RAX.
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b) You can access the lowest byte of ESI.
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c) You can access the second-to-lowest byte of RAX.
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d) You can access the second-to-lowest byte of ESI.
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8) How do you call a subroutine at 0x10,0000,0000 from code at 0x00,0010,0000?
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9) How much faster is a REL32 call instruction compared to a software interrupt or SYSCALL?
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10) How long does an IN or OUT instruction take on a 1GHz machine and on a 3GHz machine?
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11) How do you push all 16 regs?
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12) Should you put the regs in a TSS?
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13) You can have 4K or 4Meg pages in 32-bit mode. You can have 4K or what size pages in 64-bit mode?
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14) On a fresh CPU with an empty TLB, how many memory accesses (page tables) does it take to access one virtual address?
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----
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TempleOS identity-maps everything, all the time, so the usual convention of upper memory being for kernel does not apply. It uses physical addresses, basically. It puts all code in the lowest 2-Gig memory range so that it can use the CALL REL32 instruction, the fastest. It never changes privilege levels or messes with page tables, once it is up-and-running.
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----
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ANSWERS:
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1) All stack pushes and pops are 64-bits.
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2) The upper 32-bits are set to zero.
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3) To set FS or GS, you use WRMSR to write a model specific reg. See $LK,"IA32_FS_BASE",A="MN:IA32_FS_BASE"$ and $LK,"SET_FS_BASE",A="MN:SET_FS_BASE"$.
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4) Displacement addressing is now RIP relative, so RIP would be added to TSS_SOME_MEMBER. (Useless)
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5) The R13 instruction takes one more byte because it is like $LK,"REG_RBP",A="MN:REG_RBP"$ in the ModR.
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6) The R8 instruction needs a REX byte prefix to specify upper-8 reg.
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7) You can access the lowest byte of any reg. You can access AH but not the second-to-lowest byte of ESI.
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8) To call a subroutine farther than 2Gig away, you put the address into RAX, then CALL RAX.
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9) CALL REL32 is significantly faster. See $LK,"::/Demo/Lectures/InterruptDemo.HC"$.
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10) IN or OUT instructions happen at a fixed speed based on the original ISA bus clock.
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11) PUSHAD is not available for 64-bit mode, so you do it by hand.
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12) The TSS is no longer used to hold the task state because there are 16 regs and they are 64-bits, not 32-bits. I guess Intel decided doing it by hand was better than TSSes.
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13) 64-bit mode has 4K or 2Meg page size.
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14) For one access, there are 3-4 levels of page tables plus the location itself.
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@@ -0,0 +1,44 @@
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//$WW,1$You may wonder why I use "&" instead of "%".
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#define SAMPLE_SIZE 100000000
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U0 TimeIns()
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{
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I64 start1,end1,start2,end2,overhead_time,test_time;
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I64 reg i,reg tmp;
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CPURep;
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//Measure Loop Overhead
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start1=GetTSC;
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for (i=0;i<SAMPLE_SIZE;i++) {
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}
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end1=GetTSC;
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overhead_time=end1-start1;
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//Measure remainder...
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start2=GetTSC;
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for (i=0;i<SAMPLE_SIZE;i++)
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tmp=i%0x400;
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end2=GetTSC;
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test_time=end2-start2;
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"Remainder Version #1 Cycles\t: %10.5f\n",
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ToF64(test_time-overhead_time)/SAMPLE_SIZE;
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//Measure remainder...
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start2=GetTSC;
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for (i=0;i<SAMPLE_SIZE;i++)
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tmp=i&0x3FF;
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end2=GetTSC;
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test_time=end2-start2;
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"Remainder Version #2 Cycles\t: %10.5f\n",
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ToF64(test_time-overhead_time)/SAMPLE_SIZE;
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}
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TimeIns;
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/* Program Output$HL,0$$WW+H,1$$FD,1$
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8 Cores 2.660GHz
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Remainder Version #1 Cycles : 26.85345
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Remainder Version #2 Cycles : -0.00800
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$HL,1$*/
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@@ -0,0 +1,96 @@
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/*"Fixed point" means you use ints
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that are scaled by a value. A common
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example would be using number of pennies
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instead of dollars with a float.
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Fixed-point used to be much $TX,"faster",HTML="http://en.wikipedia.org/wiki/X87"$,
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but modern processors do well with
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floats. It also depends on the compiler
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and my compiler is poor with floats.
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I often use 64-bit ints with upper 32-bits
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as int and lower 32-bits as fraction.
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See $LK,"::/Demo/SubIntAccess.HC"$ for how
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to access upper or lower 32-bits.
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For a complete lst of nonstandard compiler
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features, see $LK,"::/Doc/HolyC.DD"$.
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*/
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U0 Main()
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{
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F64 t0,f_sum=0,f_val;
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I64 i ,i_sum=0,i_val;
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i_val= 2.0000002 *0x100000000;
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t0=tS;
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for (i=1000000000;i;i--)
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i_sum+=i_val;
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"Int Sum\t\t:%.9f Time:%7.3fs\n",i_sum/ToF64(0x100000000),tS-t0;
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f_val= 2.0000002;
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t0=tS;
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for (i=1000000000;i;i--)
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f_sum+=f_val;
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"Float Sum\t:%.9f Time:%7.3fs\n",f_sum,tS-t0;
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'\n';
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}
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U0 DoIt2()
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{
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I64 i=0x123456789ABCDEF0;
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"i\t\t=%X\n",i;
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"i&0xFFFFFFFF\t=%X\n",i&0xFFFFFFFF;
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"i>>32\t\t=%X\n",i>>32;
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/* Standard int types are declared
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with a special compiler feature which
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allows a structure to be accessed as a
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whole. That's why the i variable can
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be accessed normally in addition to
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structure member access $LK,"I64",A="MN:I64"$. The actual
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intrinsic compiler type is U64i.
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public U64i union I64
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{
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I8i i8[8];
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U8i u8[8];
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I16 i16[4];
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U16 u16[4];
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I32 i32[2];
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U32 u32[2];
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};
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It's not quite as great as it seems
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because the compiler decides it cannot
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place i into a reg, so there is a
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penalty.
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For a complete lst of nonstandard compiler
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features, see $LK,"::/Doc/HolyC.DD"$.
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*/
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"i.u32[0]\t=%X\n",i.u32[0];
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"i.u32[1]\t=%X\n",i.u32[1];
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}
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CPURep;
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Main;
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DoIt2;
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//See $LK,"::/Demo/Lectures/FixedPointAdvanced.HC"$
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/*Program Output$HL,0$$WW+H,1$$FD,1$
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$FG$$BG$16 Cores 3.500GHz
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Int Sum :2000000199.768690240 Time: 0.803s
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Float Sum :2000000225.656127040 Time: 3.615s
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i =123456789ABCDEF0
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i&0xFFFFFFFF =9ABCDEF0
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i>>32 =12345678
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i.u32[0] =9ABCDEF0
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i.u32[1] =12345678
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$HL,1$*/
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@@ -0,0 +1,173 @@
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/*"Fixed point" means you use ints
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that are scaled by a value. A common
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example would be using number of pennies
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instead of dollars with a float.
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Fixed-point used to be much $TX,"faster",HTML="http://en.wikipedia.org/wiki/X87"$,
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but modern processors do well with
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floats. It also depends on the compiler
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and my compiler is poor with floats.
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I often use 64-bit ints with upper 32-bits
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as int and lower 32-bits as fraction.
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See $LK,"::/Demo/SubIntAccess.HC"$ for how
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to access upper or lower 32-bits.
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*/
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#define SAMPLE_SIZE 10000000
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I32 coordinates[65536];
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asm {
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_ASM_FIXED_POINT::
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PUSH RBP
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MOV RBP,RSP
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PUSH RSI
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PUSH RDI
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MOV RSI,coordinates
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MOV RDI,ToI64(Sin(1.0)*0x100000000)
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XOR RBX,RBX //SUM
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MOV RCX,SAMPLE_SIZE-1
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@@05: XOR RDX,RDX
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MOV DX,CX
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MOVSXD RAX,U32 [RSI+RDX*4]
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IMUL RDI
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SAR RAX,32
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ADD RBX,RAX
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DEC RCX
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JGE @@05
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MOV RAX,RBX
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POP RDI
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POP RSI
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POP RBP
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RET
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SINE_VAL: DU64 Sin(1.0);
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RET_VAL: DU64 0;
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_ASM_FLOAT::
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PUSH RBP
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MOV RBP,RSP
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PUSH RSI
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MOV RSI,coordinates
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FLD U64 [SINE_VAL]
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FLDZ
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MOV RCX,SAMPLE_SIZE-1
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@@05: XOR RDX,RDX
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MOV DX,CX
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FILD U32 [RSI+RDX*4]
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FMUL ST0,ST2
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FADDP ST1,ST0
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DEC RCX
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JGE @@05
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FISTP U64 [RET_VAL]
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MOV RAX,U64 [RET_VAL]
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FFREE ST0
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FINCSTP
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POP RSI
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POP RBP
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RET
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}
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_extern _ASM_FIXED_POINT I64 AsmFixedPt();
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_extern _ASM_FLOAT I64 AsmFloat();
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U0 Main()
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{
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I64 start,end,overhead_time,test_time;
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F64 d1,fsum;
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I64 reg i,tmp,reg d2,reg sum;
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CPURep;
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//Set-up some sample coordinates
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for (i=0;i<65536;i++)
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coordinates[i]=RandU32;
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//Measure Loop Overhead
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start=GetTSC;
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for (i=SAMPLE_SIZE-1;i>=0;i--) {
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}
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end=GetTSC;
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overhead_time=end-start;
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"$$RED$$Overhead Cycles :%10.5f$$FG$$\n",
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ToF64(overhead_time)/SAMPLE_SIZE;
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//Measure F64 arithmetic
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// (Some of this is due to crappy
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// compiler code.)
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d1=Sin(1.0);
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fsum=0;
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start=GetTSC;
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for (i=SAMPLE_SIZE-1;i>=0;i--)
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fsum+=d1*coordinates[i&65535];
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end=GetTSC;
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test_time=end-start;
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"Float Sum :%X\n",ToI64(fsum);
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"$$RED$$Float Cycles :%10.5f$$FG$$\n",
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ToF64(test_time)/SAMPLE_SIZE;
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//Measure fixed point arithmetic
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d2=Sin(1.0)*0x100000000;
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sum=0;
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start=GetTSC;
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for (i=SAMPLE_SIZE-1;i>=0;i--) {
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tmp=d2*coordinates[i&65535];
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sum+=tmp.i32[1];
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}
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end=GetTSC;
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test_time=end-start;
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"Fixed-Point Sum :%X\n",sum;
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"$$RED$$Fixed-Point Cycles :%10.5f$$FG$$\n",
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ToF64(test_time)/SAMPLE_SIZE;
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//Measure fixed point arithmetic
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start=GetTSC;
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sum=AsmFixedPt;
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end=GetTSC;
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test_time=end-start;
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"Asm Fixed-Point Sum :%X\n",sum;
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"$$RED$$Asm Fixed-Point Cycles:%10.5f$$FG$$\n",
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ToF64(test_time)/SAMPLE_SIZE;
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//Measure float arithmetic
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start=GetTSC;
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sum=AsmFloat;
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end=GetTSC;
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test_time=end-start;
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"Asm Float Sum :%X\n",sum;
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"$$RED$$Asm Float Cycles :%10.5f$$FG$$\n",
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ToF64(test_time)/SAMPLE_SIZE;
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}
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Main;
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/* Program Output$HL,0$$WW+H,1$$FD,1$
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Machine 1:
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8 Cores 2.660GHz
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$FG,4$Overhead Cycles : 2.00814$FG$
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Float Sum :FFFFE1D361BEED68
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$FG,4$Float Cycles : 10.16076$FG$
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Fixed-Point Sum :FFFFE1D361729914
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$FG,4$Fixed-Point Cycles : 5.29392$FG$
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Asm Fixed-Point Sum :FFFFE1D361729914
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$FG,4$Asm Fixed-Point Cycles: 4.20464$FG$
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Asm Float Sum :FFFFE1D361BEED56
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$FG,4$Asm Float Cycles : 3.04635$FG$
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Machine 2:
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8 Cores 3.395GHz
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$FG,4$Overhead Cycles : 4.87040$FG$
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Float Sum :D20A01DB177
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$FG,4$Float Cycles : 10.11558$FG$
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Fixed-Point Sum :D209FD18CC7
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$FG,4$Fixed-Point Cycles : 4.50618$FG$
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Asm Fixed-Point Sum :D209FD18CC7
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$FG,4$Asm Fixed-Point Cycles: 3.02426$FG$
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Asm Float Sum :D20A01DB17B
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$FG,4$Asm Float Cycles : 3.21070$FG$
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$HL,1$*/
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@@ -0,0 +1,34 @@
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//This is the fastest you can update the whole scrn.
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//See $LK,"::/Demo/Lectures/MiniGrLib.HC"$ if this interests you.
|
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F64 VGAPattern(I64 p)
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{//This returns the time to update in seconds.
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F64 start=tS;
|
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I64 plane;
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for (plane=1;plane<0x10;plane<<=1) {
|
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OutU8(VGAP_IDX,VGAR_MAP_MASK);
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OutU8(VGAP_DATA,plane);
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MemSetI64(text.vga_alias,p,640*480/64);
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}
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return tS-start;
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}
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U0 GrDemo()
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{
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I64 i;
|
||||
F64 t;
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CPURep;
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for (i=0;i<16;i++) {
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t=VGAPattern(0x5555555555555555);
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"$$GREEN$$Rate:$$RED$$%5.1f FPS$$FG$$"
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" $$GREEN$$Load@30Hz:$$RED$$%5.1f%%$$FG$$\n",1/t,100*t*30.0;
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t=VGAPattern(0x3333333333333333);
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"$$GREEN$$Rate:$$RED$$%5.1f FPS$$FG$$"
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" $$GREEN$$Load@30Hz:$$RED$$%5.1f%%$$FG$$\n",1/t,100*t*30.0;
|
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}
|
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//<CTRL-ALT-v> will flush scrn VGA cache.
|
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VGAFlush;
|
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}
|
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|
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GrDemo;
|
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@@ -0,0 +1,85 @@
|
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//This is the software interrupt num
|
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//we will use. See $LK,"Software Int's",A="MN:I_WAKE"$ for
|
||||
//picking a num. Nums are subject to change.
|
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#define I_F_UNARY_MINUS I_USER
|
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asm {
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//This changes the sign of the floating
|
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//point val in RAX
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F_UNARY_MINUS_INT::
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PUSH RAX
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FLD U64 [RSP]
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FCHS
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FSTP U64 [RSP]
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||||
POP RAX
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IRET
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||||
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||||
//This does the same thing, but not as
|
||||
//an interrupt.
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||||
F_UNARY_MINUS_CALL::
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||||
PUSH RAX
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||||
FLD U64 [RSP]
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||||
FCHS
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||||
FSTP U64 [RSP]
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POP RAX
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RET
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||||
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||||
//This invokes the interrupt version
|
||||
//with a C callable function.
|
||||
_F_UM_INT::
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||||
PUSH RBP
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||||
MOV RBP,RSP
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||||
MOV RAX,SF_ARG1[RBP]
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||||
INT I_F_UNARY_MINUS
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POP RBP
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RET1 8
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||||
|
||||
//This invokes the call version
|
||||
//with a C callable function.
|
||||
_F_UM_CALL::
|
||||
PUSH RBP
|
||||
MOV RBP,RSP
|
||||
MOV RAX,SF_ARG1[RBP]
|
||||
CALL F_UNARY_MINUS_CALL
|
||||
POP RBP
|
||||
RET1 8
|
||||
}
|
||||
|
||||
_extern _F_UM_INT F64 UnaryMinusInt(F64 d);
|
||||
_extern _F_UM_CALL F64 UnaryMinusCall(F64 d);
|
||||
|
||||
#define SAMPLE_SIZE 1000000
|
||||
U0 TimeIns()
|
||||
{
|
||||
I64 start,end;
|
||||
I64 i,old_irq;
|
||||
|
||||
CPURep;
|
||||
old_irq=IntEntrySet(I_F_UNARY_MINUS,F_UNARY_MINUS_INT,IDTET_TRAP);
|
||||
|
||||
//Measure interrupt time
|
||||
start=GetTSC;
|
||||
for (i=0;i<SAMPLE_SIZE;i++)
|
||||
UnaryMinusInt(ã);
|
||||
end=GetTSC;
|
||||
"Interrupt Cycles: %10.5f\n",ToF64(end-start)/SAMPLE_SIZE;
|
||||
|
||||
//Measure call time
|
||||
start=GetTSC;
|
||||
for (i=0;i<SAMPLE_SIZE;i++)
|
||||
UnaryMinusCall(ã);
|
||||
end=GetTSC;
|
||||
"Call Cycles: %10.5f\n",ToF64(end-start)/SAMPLE_SIZE;
|
||||
|
||||
IntEntrySet(I_F_UNARY_MINUS,old_irq,IDTET_IRQ);
|
||||
}
|
||||
|
||||
TimeIns;
|
||||
|
||||
/* Program Output$HL,0$$WW+H,1$$FD,1$
|
||||
$PT$$FG$$BG$6 Cores 3.395GHz
|
||||
Interrupt Cycles: 573.98543
|
||||
Call Cycles: 9.74349
|
||||
$HL,1$*/
|
||||
@@ -0,0 +1,236 @@
|
||||
/*$WW,1$
|
||||
$TR-C,"Main Compiler"$
|
||||
$ID,2$The mini compiler is like the main compiler, except the main compiler's lexical analyser removes comments and does preprocessing. $LK,"Lex",A="MN:Lex"$(),$LK,"Echo",A="MN:Echo"$(ON).
|
||||
|
||||
The main compiler generates $LK,"Intermediate Code",A="FF:::/Compiler/CompilerA.HH,IC_END"$ at the parser stage. See $LK,"PrsExpression",A="MN:PrsExpression"$(), $LK,"PrsStmt",A="MN:PrsStmt"$().
|
||||
|
||||
The main compiler optimizes See $LK,"Intermediate Code Attributes",A="MN:intermediate_code_table"$, $LK,"Combining Consts",A="FF:::/Compiler/OptPass012.HC,case IC_MUL"$, $LK,"Choosing Reg Vars",A="FF:::/Compiler/OptPass3.HC,cmp.num_reg_vars"$. Use $LK,"PassTrace",A="MN:PassTrace"$() to see the optimization stages.
|
||||
|
||||
The main compiler makes machine code in the back end. See $LK,"IC Struct",A="MN:CIntermediateCode"$, $LK,"COCCompile",A="MN:COCCompile"$ and $LK,"OptPass789A",A="FF:::/Compiler/OptPass789A.HC,IC_MUL"$(), $LK,"BackEnd",A="FF:::/Compiler/BackA.HC,ICMul"$. Set $LK,"Trace",A="MN:Trace"$(ON) to see the output of the backend.
|
||||
$ID,-2$
|
||||
$TR-C,"Mini Compiler"$
|
||||
$ID,2$For this mini compiler, some things you should know about 64-bit asm:
|
||||
|
||||
* Putting a 0x48, known as the REX byte, in front of an inst makes it 64-bit size.
|
||||
|
||||
* "PUSH EAX", "POP EAX" and "XOR EAX,EAX" will behave as 64-bit even without REX because the stk is always 64 bit and because the XOR clears the upper 32-bits.
|
||||
|
||||
It is okay in TempleOS to change RAX, RBX, RCX, RDX, R8 and R9 without restoring them to their original values.
|
||||
$ID,-2$$WW,0$*/
|
||||
|
||||
#define TK_EOF 0
|
||||
#define TK_NUM 1
|
||||
#define TK_OP 2
|
||||
#define TK_LEFT 3
|
||||
#define TK_RIGHT 4
|
||||
|
||||
#define OP_MUL 1
|
||||
#define OP_DIV 2
|
||||
#define OP_ADD 3
|
||||
#define OP_SUB 4
|
||||
|
||||
I64 Lex(U8 **_src,I64 *num)
|
||||
{//See $LK,"Lex",A="MN:Lex"$().
|
||||
U8 *src=*_src;
|
||||
I64 i;
|
||||
while (TRUE) {
|
||||
switch (*src) {
|
||||
case 0:
|
||||
case ';':
|
||||
*_src=src;
|
||||
return TK_EOF;
|
||||
case CH_SPACE:
|
||||
case '\r':
|
||||
case '\n':
|
||||
src++;
|
||||
break;
|
||||
case '0'...'9':
|
||||
i=0;
|
||||
do {
|
||||
i=i*10+*src-'0';
|
||||
src++;
|
||||
} while ('0'<=*src<='9');
|
||||
*num=i;
|
||||
*_src=src;
|
||||
return TK_NUM;
|
||||
case '*':
|
||||
*num=OP_MUL;
|
||||
*_src=src+1;
|
||||
return TK_OP;
|
||||
case '/':
|
||||
*num=OP_DIV;
|
||||
*_src=src+1;
|
||||
return TK_OP;
|
||||
case '+':
|
||||
*num=OP_ADD;
|
||||
*_src=src+1;
|
||||
return TK_OP;
|
||||
case '-':
|
||||
*num=OP_SUB;
|
||||
*_src=src+1;
|
||||
return TK_OP;
|
||||
case '(':
|
||||
*_src=src+1;
|
||||
return TK_LEFT;
|
||||
case ')':
|
||||
*_src=src+1;
|
||||
return TK_RIGHT;
|
||||
default:
|
||||
throw;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#define PREC_EOF 0
|
||||
#define PREC_TERM 1
|
||||
#define PREC_MUL 2
|
||||
#define PREC_ADD 3
|
||||
#define PREC_PAREN 4
|
||||
|
||||
extern I64 Parse(U8 **_src,U8 **_dst);
|
||||
|
||||
U0 PrsTerm(U8 **_src,U8 **_dst,I64 prec)
|
||||
{//See $LK,"PrsExpression",A="MN:PrsExpression"$().
|
||||
I64 i;
|
||||
U8 *src2;
|
||||
U8 *dst2;
|
||||
if (Parse(_src,_dst)==PREC_TERM) {
|
||||
src2=*_src;
|
||||
dst2=*_dst;
|
||||
while (TRUE) {
|
||||
//This is inefficient. The main compiler doesn't back-up like this.
|
||||
i=Parse(&src2,&dst2);
|
||||
if (PREC_MUL<=i<prec) {
|
||||
*_src=src2;
|
||||
*_dst=dst2;
|
||||
} else
|
||||
break;
|
||||
}
|
||||
} else
|
||||
throw;
|
||||
}
|
||||
|
||||
I64 Parse(U8 **_src,U8 **_dst)
|
||||
{//See $LK,"PrsExpression",A="MN:PrsExpression"$().
|
||||
//See $LK,"Opcode Fmts",A="FF:::/Compiler/OpCodes.DD,IDIV"$ for details on asm insts.
|
||||
I64 i;
|
||||
U8 *dst=*_dst;
|
||||
switch (Lex(_src,&i)) {
|
||||
case TK_EOF:
|
||||
*dst++=0x58; //POP RAX
|
||||
*dst++=0xC3; //RET
|
||||
*_dst=dst;
|
||||
return PREC_EOF;
|
||||
case TK_NUM:
|
||||
*dst++=0x48; //REX
|
||||
*dst++=0xB8; //MOV RAX,immediate num
|
||||
*dst(I64 *)++=i;
|
||||
|
||||
*dst++=0x50; //PUSH RAX
|
||||
*_dst=dst;
|
||||
return PREC_TERM;
|
||||
case TK_LEFT:
|
||||
PrsTerm(_src,_dst,PREC_PAREN);
|
||||
if (Parse(_src,_dst)!=PREC_PAREN)
|
||||
throw;
|
||||
return PREC_TERM;
|
||||
case TK_RIGHT:
|
||||
return PREC_PAREN;
|
||||
case TK_OP:
|
||||
switch (i) {
|
||||
case OP_MUL:
|
||||
PrsTerm(_src,&dst,PREC_MUL);
|
||||
*dst++=0x5A; //POP RDX
|
||||
*dst++=0x58; //POP RAX
|
||||
|
||||
*dst++=0x48; //REX
|
||||
*dst++=0x0F;
|
||||
*dst++=0xAF; //IMUL RAX,RDX
|
||||
*dst++=0xC2;
|
||||
|
||||
*dst++=0x50; //PUSH RAX
|
||||
*_dst=dst;
|
||||
return PREC_MUL;
|
||||
case OP_DIV:
|
||||
PrsTerm(_src,&dst,PREC_MUL);
|
||||
*dst++=0x5B; //POP RBX
|
||||
*dst++=0x58; //POP RAX
|
||||
|
||||
*dst++=0x33; //XOR RDX,RDX
|
||||
*dst++=0xD2;
|
||||
|
||||
*dst++=0x48; //REX
|
||||
*dst++=0xF7; //IDIV RBX
|
||||
*dst++=0xFB;
|
||||
|
||||
*dst++=0x50; //PUSH RAX
|
||||
*_dst=dst;
|
||||
return PREC_MUL;
|
||||
case OP_ADD:
|
||||
PrsTerm(_src,&dst,PREC_ADD);
|
||||
*dst++=0x5A; //POP RDX
|
||||
*dst++=0x58; //POP RAX
|
||||
|
||||
*dst++=0x48; //REX
|
||||
*dst++=0x03; //ADD RAX,RDX
|
||||
*dst++=0xC2;
|
||||
|
||||
*dst++=0x50; //PUSH RAX
|
||||
*_dst=dst;
|
||||
return PREC_ADD;
|
||||
case OP_SUB:
|
||||
PrsTerm(_src,&dst,PREC_ADD);
|
||||
*dst++=0x5A; //POP RDX
|
||||
*dst++=0x58; //POP RAX
|
||||
|
||||
*dst++=0x48; //REX
|
||||
*dst++=0x2B; //SUB RAX,RDX
|
||||
*dst++=0xC2;
|
||||
|
||||
*dst++=0x50; //PUSH RAX
|
||||
*_dst=dst;
|
||||
return PREC_ADD;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
U0 Main()
|
||||
{
|
||||
U8 *src,*src2,*code,*dst;
|
||||
|
||||
//Fixed size, no buffer overrun check.
|
||||
//You can make it fancier if you like.
|
||||
code=MAlloc(512,Fs->code_heap);
|
||||
|
||||
while (TRUE) {
|
||||
"This will compile an expression\n"
|
||||
"consisting of ints, parentheses\n"
|
||||
"and the operators +,-,* and /.\n";
|
||||
src=GetStr;
|
||||
if (*src) {
|
||||
src2=src;
|
||||
dst=code;
|
||||
try {
|
||||
PrsTerm(&src2,&dst,PREC_PAREN);
|
||||
if (Parse(&src2,&dst)!=PREC_EOF)
|
||||
throw;
|
||||
"$$RED$$This code is not efficient, but the compiler is simple.$$FG$$\n";
|
||||
Un(code,dst-code); //Unassemble the code we created.
|
||||
//$LK,"Call",A="MN:Call"$() is a function. See $LK,"_CALL",A="FF:::/Kernel/KUtils.HC,_CALL"$::
|
||||
//See also $LK,"CallInd",A="MN:CallInd"$(). See $LK,"_CALL_IND",A="FF:::/Kernel/KUtils.HC,_CALL_IND"$::
|
||||
"$$LTBLUE$$Answer:%d$$FG$$\n",Call(code);
|
||||
} catch {
|
||||
"$$RED$$Error$$FG$$\n";
|
||||
PutExcept;
|
||||
}
|
||||
Free(src);
|
||||
} else {
|
||||
Free(src);
|
||||
break;
|
||||
}
|
||||
}
|
||||
Free(code);
|
||||
}
|
||||
|
||||
Main;
|
||||
|
||||
@@ -0,0 +1,132 @@
|
||||
//See $LK,"::/Demo/Lectures/GraphicsCPULoad.HC"$
|
||||
U8 rev[256], //The VGA bits are bwd
|
||||
|
||||
image[640*480/8]; //We need read-modify write.
|
||||
//0xA0000 alias memory can't be read.
|
||||
|
||||
U0 MGInit()
|
||||
{
|
||||
I64 i,j;
|
||||
MemSet(image,0,sizeof(image));
|
||||
MemSet(rev,0,sizeof(rev));
|
||||
for (i=0;i<256;i++)
|
||||
for (j=0;j<8;j++)
|
||||
if (Bt(&i,j))
|
||||
Bts(&rev[i],7-j);
|
||||
}
|
||||
|
||||
U0 MGUpdate()
|
||||
{//Copy image to VGA memory
|
||||
//For better performance we could only write what's changed.
|
||||
//0xA0000 alias is slower than normal RAM.
|
||||
OutU8(VGAP_IDX,VGAR_MAP_MASK);
|
||||
OutU8(VGAP_DATA,0xF);//All color planes at once -- Black and White
|
||||
MemCpy(text.vga_alias,image,sizeof(image)); //Alias of 0xA0000
|
||||
}
|
||||
|
||||
U0 MGPlot(I64 x,I64 y)
|
||||
{
|
||||
if (0<=x<640 && 0<=y<480)
|
||||
Bts(image,y*640+x^7);
|
||||
}
|
||||
|
||||
U0 MGHLine(I64 x1,I64 x2,I64 y)
|
||||
{//Warning! No clipping
|
||||
//For performance, we do as many whole-bytes as possible.
|
||||
U8 *ptr;
|
||||
I64 i,w,leading,trailing,whole_bytes;
|
||||
if (x2<x1) SwapI64(&x1,&x2);
|
||||
ptr=image+y*640/8+x1>>3;
|
||||
w=x2-x1+1;
|
||||
leading =8-x1&7;
|
||||
trailing=(x2+1)&7;
|
||||
if (leading+trailing>w)
|
||||
*ptr|=rev[(0xFF00>>leading&(0x00FF<<trailing)>>8)];
|
||||
else {
|
||||
whole_bytes=(w-leading-trailing)>>3;
|
||||
if (leading)
|
||||
*ptr++|=rev[(0xFF00>>leading)&0xFF];
|
||||
for (i=0;i<whole_bytes;i++)
|
||||
*ptr++=0xFF;
|
||||
if (trailing)
|
||||
*ptr++|=rev[(0x00FF<<trailing)>>8];
|
||||
}
|
||||
}
|
||||
|
||||
U0 MGLine(I64 x1,I64 y1,I64 x2,I64 y2)
|
||||
{//Warning! No clipping
|
||||
I64 dx=x2-x1,dy=y2-y1;
|
||||
x1<<=32; x2<<=32;
|
||||
y1<<=32; y2<<=32;
|
||||
if (AbsI64(dx)>AbsI64(dy)) {
|
||||
dy=dy<<32/AbsI64(dx);
|
||||
dx=SignI64(dx)<<32;
|
||||
while (x1!=x2) {
|
||||
MGPlot(x1.i32[1],y1.i32[1]);
|
||||
x1+=dx; y1+=dy;
|
||||
}
|
||||
} else {
|
||||
dx=dx<<32/AbsI64(dy);
|
||||
dy=SignI64(dy)<<32;
|
||||
while (y1!=y2) {
|
||||
MGPlot(x1.i32[1],y1.i32[1]);
|
||||
x1+=dx; y1+=dy;
|
||||
}
|
||||
}
|
||||
MGPlot(x1.i32[1],y1.i32[1]);
|
||||
}
|
||||
|
||||
U0 MGCircle(I64 x,I64 y,F64 r)
|
||||
{
|
||||
F64 s,c,x1,y1,x2,y2;
|
||||
I64 len;
|
||||
if (r<0) return;
|
||||
x1=r; y1=0;
|
||||
c=Cos(1/r);
|
||||
s=Sin(1/r);
|
||||
len=2*r*ã;
|
||||
MGPlot(x+x1,y+y1);
|
||||
while (len-->=0) {
|
||||
|
||||
//m1@a1 * m2@a2 = m1*m2@(arg1+arg2)
|
||||
|
||||
//(x1+y1i)*(x2+y2i) = x1*x2+(x1*y1+x2*y2)i-y1*y2
|
||||
|
||||
// me$SY,-3$ti$SY,0$=mCos(t)+imSin(t)
|
||||
|
||||
x2=x1; y2=y1;
|
||||
x1=c*x2-s*y2;
|
||||
y1=s*x2+c*y2;
|
||||
MGPlot(x+x1,y+y1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
U0 MiniGrLibDemo()
|
||||
{
|
||||
I64 i;
|
||||
MGInit;
|
||||
|
||||
for (i=0;i<100;i++)
|
||||
MGHLine(200+i,400+i,300+i);
|
||||
for (i=0;i<500;i+=10)
|
||||
MGLine(i,0,0,480-i);
|
||||
for (i=0;i<300;i+=4)
|
||||
MGCircle(200,100+i,i);
|
||||
MGUpdate;
|
||||
Busy(1500000);
|
||||
/*
|
||||
We are returning graphics to normal operations under TempleOS.
|
||||
It is not normal to by-pass the TempleOS graphcis routines.
|
||||
The TempleOS graphics don't know VGA has changed.
|
||||
This bit tells TempleOS to update whole scrn.
|
||||
*/
|
||||
//<CTRL-ALT-v> will flush scrn VGA cache.
|
||||
VGAFlush;
|
||||
}
|
||||
|
||||
MiniGrLibDemo;
|
||||
|
||||
//See $LK,"RawPutChar",A="MN:RawPutChar"$() for text.
|
||||
//See $LK,"::/Demo/Lectures/ScrnMemory.HC"$ for color.
|
||||
//See $LK,"::/Demo/Lectures/GraphicsCPULoad.HC"$.
|
||||
@@ -0,0 +1,56 @@
|
||||
class Person
|
||||
{
|
||||
U8 first [32];
|
||||
U8 last [32];
|
||||
U8 address1 [64];
|
||||
U8 address2 [64];
|
||||
U8 city [32];
|
||||
U8 state_zip[32];
|
||||
};
|
||||
|
||||
U0 OffsetDemo1()
|
||||
{
|
||||
Person *p=MAlloc(sizeof(Person));
|
||||
StrCpy(p->first, "Terry");
|
||||
StrCpy(p->last, "Davis");
|
||||
StrCpy(p->address1, "8144 Sickle Lane");
|
||||
StrCpy(p->address2, "");
|
||||
StrCpy(p->city, "Las Vegas");
|
||||
StrCpy(p->state_zip,"NV 89128");
|
||||
}
|
||||
|
||||
U(&OffsetDemo1,34);
|
||||
PressAKey;
|
||||
|
||||
/*
|
||||
|
||||
x86 has signed 8-bit displacements
|
||||
and signed 32-bit displacements.
|
||||
|
||||
This example uses 8-bit negative displacements.
|
||||
|
||||
*/
|
||||
|
||||
class Person
|
||||
{ $$=-128;
|
||||
U8 first [32];
|
||||
U8 last [32];
|
||||
U8 address1 [64];
|
||||
U8 address2 [64];
|
||||
U8 city [32];
|
||||
U8 state_zip[32];
|
||||
};
|
||||
|
||||
U0 OffsetDemo2()
|
||||
{
|
||||
Person *p=MAlloc(sizeof(Person))(I64)+128;
|
||||
StrCpy(p->first, "Terry");
|
||||
StrCpy(p->last, "Davis");
|
||||
StrCpy(p->address1, "8144 Sickle Lane");
|
||||
StrCpy(p->address2, "");
|
||||
StrCpy(p->city, "Las Vegas");
|
||||
StrCpy(p->state_zip,"NV 89128");
|
||||
}
|
||||
|
||||
U(&OffsetDemo2,34);
|
||||
PressAKey;
|
||||
@@ -0,0 +1,108 @@
|
||||
/*The moral of this story is simple
|
||||
inst level optimizations
|
||||
don't matter much on a modern Intel CPU
|
||||
because they convert complex insts
|
||||
to a stream of RISC insts.
|
||||
|
||||
I learned this the hard way when I thought
|
||||
I was greatly improving my compiler by
|
||||
cutting code by a third. No significant
|
||||
speed-up. Depressing.
|
||||
*/
|
||||
|
||||
#define SAMPLES (8*10000000+1)
|
||||
|
||||
asm {
|
||||
|
||||
LIMIT:: DU64 SAMPLES; //Memory reference should be bad, right?
|
||||
|
||||
_BADLY_UNOPTIMIZED::
|
||||
MOV RAX,0
|
||||
MOV RCX,1
|
||||
@@05: MOV RDX,RCX
|
||||
INC RCX //if no dependencies, Free!
|
||||
ADD RAX,RDX
|
||||
MOV RDX,LIMIT-16 //added 16 displacement to make it worse
|
||||
CMP RCX,U64 16[RDX]
|
||||
JB @@05
|
||||
RET
|
||||
|
||||
_WELL_OPTIMIZED1::
|
||||
XOR RAX,RAX
|
||||
MOV RCX,SAMPLES-1
|
||||
@@05: ADD RAX,RCX
|
||||
DEC RCX
|
||||
JNZ @@05
|
||||
RET
|
||||
|
||||
_WELL_OPTIMIZED2:: //Unrolled
|
||||
XOR RAX,RAX
|
||||
MOV RCX,SAMPLES-1
|
||||
@@05: ADD RAX,RCX
|
||||
DEC RCX
|
||||
ADD RAX,RCX
|
||||
DEC RCX
|
||||
ADD RAX,RCX
|
||||
DEC RCX
|
||||
ADD RAX,RCX
|
||||
DEC RCX
|
||||
ADD RAX,RCX
|
||||
DEC RCX
|
||||
ADD RAX,RCX
|
||||
DEC RCX
|
||||
ADD RAX,RCX
|
||||
DEC RCX
|
||||
ADD RAX,RCX
|
||||
DEC RCX
|
||||
JNZ @@05
|
||||
RET
|
||||
|
||||
_WELL_OPTIMIZED3::
|
||||
XOR RAX,RAX
|
||||
MOV RCX,SAMPLES-1
|
||||
@@05: ADD RAX,RCX
|
||||
LOOP @@05 //Inst has slow speed, but saves code size.
|
||||
RET
|
||||
}
|
||||
|
||||
_extern _BADLY_UNOPTIMIZED I64 Loop1();
|
||||
_extern _WELL_OPTIMIZED1 I64 Loop2();
|
||||
_extern _WELL_OPTIMIZED2 I64 Loop3();
|
||||
_extern _WELL_OPTIMIZED3 I64 Loop4();
|
||||
|
||||
I64 i;
|
||||
F64 t0;
|
||||
|
||||
CPURep;
|
||||
|
||||
"Bad Code\n";
|
||||
t0=tS;
|
||||
i=Loop1;
|
||||
"Res:%d Time:%9.6f\n",i,tS-t0;
|
||||
|
||||
"Good Code #1\n";
|
||||
t0=tS;
|
||||
i=Loop2;
|
||||
"Res:%d Time:%9.6f\n",i,tS-t0;
|
||||
|
||||
"Good Code #2\n";
|
||||
t0=tS;
|
||||
i=Loop3;
|
||||
"Res:%d Time:%9.6f\n",i,tS-t0;
|
||||
|
||||
"Good Code #3\n";
|
||||
t0=tS;
|
||||
i=Loop4;
|
||||
"Res:%d Time:%9.6f\n",i,tS-t0;
|
||||
|
||||
/* Program Output$HL,0$$WW+H,1$$FD,1$
|
||||
8 Cores 2.660GHz
|
||||
Bad Code
|
||||
Res:3200000040000000 Time: 0.069966
|
||||
Good Code #1
|
||||
Res:3200000040000000 Time: 0.062567
|
||||
Good Code #2
|
||||
Res:3200000040000000 Time: 0.062907
|
||||
Good Code #3
|
||||
Res:3200000040000000 Time: 0.156359
|
||||
$HL,1$*/
|
||||
@@ -0,0 +1,73 @@
|
||||
//See $LK,"PCI",A="HI:PCI"$.
|
||||
|
||||
#if mp_cnt>1
|
||||
#define DEST_CPU 1
|
||||
#else
|
||||
#define DEST_CPU 0
|
||||
#endif
|
||||
|
||||
#assert I_USER==0x40
|
||||
|
||||
interrupt U0 IntMy40()
|
||||
{
|
||||
lock {progress1++;}
|
||||
*(dev.uncached_alias+LAPIC_EOI)(U32 *)=0;
|
||||
}
|
||||
|
||||
interrupt U0 IntMy41()
|
||||
{
|
||||
lock {progress2++;}
|
||||
*(dev.uncached_alias+LAPIC_EOI)(U32 *)=0;
|
||||
}
|
||||
|
||||
interrupt U0 IntMy42()
|
||||
{
|
||||
lock {progress3++;}
|
||||
*(dev.uncached_alias+LAPIC_EOI)(U32 *)=0;
|
||||
}
|
||||
|
||||
interrupt U0 IntMy43()
|
||||
{
|
||||
lock {progress4++;}
|
||||
*(dev.uncached_alias+LAPIC_EOI)(U32 *)=0;
|
||||
}
|
||||
|
||||
I64 vect[4]={&IntMy40,&IntMy41,&IntMy42,&IntMy43};
|
||||
|
||||
U0 Main()
|
||||
{
|
||||
I64 i;
|
||||
U8 *da=dev.uncached_alias+IOAPIC_REG;
|
||||
U32 *_d=dev.uncached_alias+IOAPIC_DATA;
|
||||
|
||||
ProgressBarsRst;
|
||||
for (i=I_USER;i<I_USER+4;i++)
|
||||
IntEntrySet(i,vect[i&3],IDTET_IRQ);
|
||||
|
||||
//There are like 4*6 vects. Bus zero
|
||||
//has the first four vects.
|
||||
for (i=IOREDTAB;i<IOREDTAB+4*2;i+=2) {
|
||||
*da=i+1;
|
||||
*_d=dev.mp_apic_ids[DEST_CPU]<<24;
|
||||
*da=i;
|
||||
*_d=0x4000+0x40+(i-IOREDTAB)/2;
|
||||
}
|
||||
|
||||
Sleep(1000);
|
||||
"The keyboard and timer seem to be active.\n"
|
||||
"IntA:%d IntB:%d IntC:%d IntD:%d\n\n"
|
||||
"IntB is my keybaord and regs a single KEY-UP.\n"
|
||||
"Rerun and press a few keys.\n",
|
||||
progress1,progress2,progress3,progress4;
|
||||
|
||||
//Disable vects
|
||||
for (i=IOREDTAB;i<IOREDTAB+4*2;i+=2) {
|
||||
*da=i+1;
|
||||
*_d=dev.mp_apic_ids[DEST_CPU]<<24;
|
||||
*da=i;
|
||||
*_d=0x14000+0x40+(i-IOREDTAB)/2;
|
||||
}
|
||||
ProgressBarsRst;
|
||||
}
|
||||
|
||||
Main;
|
||||
@@ -0,0 +1,75 @@
|
||||
/*TempleOS runs exclusively in ring 0.
|
||||
Ring 0 is part of the $LK,"Charter",A="FI:::/Doc/Charter.DD"$.
|
||||
This demo is for you to play around
|
||||
with ring 3. TempleOS is for
|
||||
recreational programming, after all.
|
||||
|
||||
This redirects the general protection
|
||||
fault, switches to ring 3, and generates
|
||||
a fault to switch back.
|
||||
*/
|
||||
|
||||
U8 *old_stk,*new_rip;
|
||||
|
||||
asm {
|
||||
INT_TO_RING0:: //Set to handle general protection 0xD fault temporarily.
|
||||
INC U64 [SYS_PROGRESS1]
|
||||
PUSH U32 CGDT.ds //STKSEG
|
||||
MOV RAX,U64 [&old_stk]
|
||||
PUSH RAX
|
||||
PUSH U32 0 //FLAGS--interrupts off
|
||||
PUSH U32 CGDT.cs64
|
||||
MOV RAX,U64 [&new_rip]
|
||||
PUSH RAX
|
||||
IRET
|
||||
}
|
||||
|
||||
U0 Ring3Demo()
|
||||
{
|
||||
U8 *old_vect;
|
||||
"Progress1 Before:%X\n",progress1;
|
||||
CLI
|
||||
old_vect=IntEntrySet(0x0D,INT_TO_RING0,IDTET_TRAP,0);
|
||||
|
||||
TSSBusy(Gs->tss->tr_ring3,OFF);
|
||||
SetRAX(Gs->tss->tr_ring3+3);
|
||||
LTR AX
|
||||
|
||||
asm {
|
||||
MOV U64 [&old_stk],RSP
|
||||
|
||||
LEA RAX,[R3_CALLBACK]
|
||||
MOV U64 [&new_rip],RAX
|
||||
|
||||
MOV AX,CGDT.ds_ring3+3
|
||||
MOV DS,AX
|
||||
MOV ES,AX
|
||||
|
||||
PUSH U32 CGDT.ds_ring3+3 //STKSEG
|
||||
PUSH U64 [&old_stk]
|
||||
PUSH U32 0 //FLAGS--interrupts off
|
||||
PUSH U32 CGDT.cs64_ring3+3
|
||||
LEA RAX,[R3_START]
|
||||
PUSH RAX
|
||||
IRET
|
||||
|
||||
R3_START:
|
||||
INC U64 [SYS_PROGRESS1]
|
||||
CLI //This causes general protection fault #13
|
||||
|
||||
R3_CALLBACK:
|
||||
MOV AX,CGDT.ds
|
||||
MOV DS,AX
|
||||
MOV ES,AX
|
||||
}
|
||||
|
||||
TSSBusy(Gs->tss->tr,OFF);
|
||||
SetRAX(Gs->tss->tr);
|
||||
LTR AX
|
||||
|
||||
IntEntrySet(0x0D,old_vect,IDTET_IRQ,0);
|
||||
STI
|
||||
"Progress1 After :%X\n",progress1;
|
||||
}
|
||||
|
||||
Ring3Demo;
|
||||
@@ -0,0 +1,49 @@
|
||||
//This just shows how scrn memory works.
|
||||
//See $LK,"::/Demo/Lectures/MiniGrLib.HC"$
|
||||
|
||||
U0 PlotXY(I64 x,I64 y)
|
||||
{
|
||||
//Scrn bits are revd
|
||||
LBts(text.vga_alias,y*GR_WIDTH+x^7);
|
||||
}
|
||||
|
||||
U0 Main()
|
||||
{
|
||||
I64 i;
|
||||
//This makes all 4 color planes active.
|
||||
OutU8(VGAP_IDX,VGAR_MAP_MASK);
|
||||
OutU8(VGAP_DATA,WHITE);
|
||||
MemSet(text.vga_alias,0,GR_WIDTH*GR_HEIGHT/8);
|
||||
|
||||
OutU8(VGAP_IDX,VGAR_MAP_MASK);
|
||||
OutU8(VGAP_DATA,RED);
|
||||
for (i=0;i<200;i++)
|
||||
PlotXY(i,i);
|
||||
|
||||
OutU8(VGAP_IDX,VGAR_MAP_MASK);
|
||||
OutU8(VGAP_DATA,GREEN);
|
||||
for (i=0;i<200;i++)
|
||||
PlotXY(100,i);
|
||||
|
||||
OutU8(VGAP_IDX,VGAR_MAP_MASK);
|
||||
OutU8(VGAP_DATA,BLUE);
|
||||
for (i=0;i<200;i++)
|
||||
PlotXY(200-i,i);
|
||||
/*If you want a mixed color sel multiple planes
|
||||
but you have to be sure the unseled planes
|
||||
are zero, so sel them and make them zero.
|
||||
You can't do reads on VGA memory, by the way.
|
||||
That means no read-modify-writes, too.
|
||||
*/
|
||||
Busy(4000000);
|
||||
|
||||
//TempleOS has a 4 plane memory duplicate of the scrn, $LK,"gr.scrn_image",A="MN:CGrGlbls"$,
|
||||
//and only writes actual changes. See $LK,"GrUpdateVGAGraphics",A="MN:GrUpdateVGAGraphics"$().
|
||||
//<CTRL-ALT-v> will flush scrn VGA cache.
|
||||
VGAFlush;
|
||||
}
|
||||
|
||||
Main;
|
||||
|
||||
//See $LK,"::/Demo/Lectures/GraphicsCPULoad.HC"$.
|
||||
|
||||
Reference in new issue
Block a user