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TempleOSCDV4.10.ISO

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This commit is contained in:
Terry A. Davis authored and minexew committed 2018-09-08 21:47:44 +02:00
1 parent c5954d3371
commit 9206246147
181 files changed
+4468 -4313
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Kernel/Mem/HeapCtrl.CPP
+1 -1
View File
@@ -1,6 +1,6 @@
CHeapCtrl *HeapCtrlInit(CHeapCtrl *hc=NULL,CTask *task=NULL,CBlkPool *bp)
{//See $LK,"HeapLog",A="MN:HeapLog"$() for an example.
//Duplicated for $LK,"Adam Task",A="FF:::/Kernel/KStart.CPP,CHeapCtrl.bp"$.
//Duplicated for $LK,"Adam Task",A="FF:::/Kernel/KStart64.CPP,CHeapCtrl.bp"$.
if (!hc)
hc=ACAlloc(sizeof(CHeapCtrl));
hc->hc_signature=HEAP_CTRL_SIGNATURE_VAL;
Kernel/Mem/Mem512.CPP
+3 -2
View File
@@ -57,7 +57,7 @@ Return: NULL if out of memory.
} while (i<64-MEM_PAGE_BITS-1);
pages512=0;
res=NULL; //Out of memory
goto at_done;
goto at_done2;
}
if (res->pages<pages512)
m=res;
@@ -74,7 +74,8 @@ Return: NULL if out of memory.
}
}
at_done:
bp->used_u8s+=pages512<<MEM_PAGE_BITS;
bp->used_u8s+=res->pages<<MEM_PAGE_BITS;
at_done2:
LBtr(&bp->locked_flags,BPlf_LOCKED);
POPFD
return res;
Kernel/Mem/MemPhysical.CPP
+37 -27
View File
@@ -1,7 +1,7 @@
Bool Mem32DevIns(CMemRange *tempmr)
{
CMemRange *tempmr1=dev.mem32_root.next,*tempmr2;
while (tempmr1!=&dev.mem32_root) {
CMemRange *tempmr1=dev.mem32_head.next,*tempmr2;
while (tempmr1!=&dev.mem32_head) {
if (!tempmr1->type && tempmr->base>=tempmr1->base &&
tempmr->base+tempmr->size<=tempmr1->base+tempmr1->size) {
if (tempmr->base>tempmr1->base) {
@@ -32,14 +32,14 @@ U0 Mem32DevInit()
CMemRange *tempmr;
CMemE820 *m20=SYS_MEM_E820;
QueInit(&dev.mem32_root);
QueInit(&dev.mem32_head);
tempmr=AMAlloc(sizeof(CMemRange));
tempmr->type=MRT_UNUSED;
tempmr->flags=0;
//Maybe !!! Change this to 0xF0000000 !!!
tempmr->base=0xE0000000;
tempmr->size=0x10000000;
QueIns(tempmr,dev.mem32_root.last);
QueIns(tempmr,dev.mem32_head.last);
if (m20->type) {
while (m20->type) {
@@ -67,10 +67,13 @@ U0 MemPagesNotPresentMark()
m20++;
}
if (max_physical>=0x1000000+m01[1]<<16) {
a=(max_physical+0x1FFFFF)&~0x1FFFFF;
if (sys_gig_pages)
a=(max_physical+0x3FFFFFFF)&~0x3FFFFFFF;
else
a=(max_physical+0x1FFFFF)&~0x1FFFFF;
while (a<MEM_MAPPED_SPACE) {
MemPagePresentMark(a,FALSE);
a+=0x200000;
a+=MemPageSize(a);
}
}
}
@@ -83,8 +86,8 @@ U8 *Mem32DevAlloc(I64 size,I64 alignment)
CMemRange *tempmr,*tempmr1;
while (LBts(&sys_semas[SYS_SEMA_DEV_MEM],0))
Yield;
tempmr1=dev.mem32_root.next;
while (tempmr1!=&dev.mem32_root) {
tempmr1=dev.mem32_head.next;
while (tempmr1!=&dev.mem32_head) {
base=(tempmr1->base+alignment-1)&~(alignment-1);
limit=base+size-1;
if (!tempmr1->type &&
@@ -114,8 +117,8 @@ U0 Mem32DevFree(U8 *base)
if (!base) return;
while (LBts(&sys_semas[SYS_SEMA_DEV_MEM],0))
Yield;
tempmr=dev.mem32_root.next;
while (tempmr!=&dev.mem32_root) {
tempmr=dev.mem32_head.next;
while (tempmr!=&dev.mem32_head) {
if (tempmr->base==base) {
tempmr->type=MRT_UNUSED;
break;
@@ -125,40 +128,47 @@ U0 Mem32DevFree(U8 *base)
LBtr(&sys_semas[SYS_SEMA_DEV_MEM],0);
}
U8 *Mem64DevAlloc(I64 *_pages2Meg)
U8 *Mem64DevAlloc(I64 *_pages1Gig)
{//Alloc 64-bit addr space for device.
U8 *res;
I64 i=*_pages2Meg,*pte;
U8 *a;
I64 i=*_pages1Gig,*pte;
while (LBts(&sys_semas[SYS_SEMA_DEV_MEM],0))
Yield;
while (i--) {
dev.mem64_ptr-=0x200000;
pte=MemPageTable(dev.mem64_ptr);
*pte=*pte&~0x18 |0x11; //Uncached and present
InvlPg(dev.mem64_ptr);
a=dev.mem64_ptr-=1<<30;
do {
pte=MemPageTable(a);
*pte=*pte&~0x18 |0x11; //Uncached and present
InvlPg(dev.mem64_ptr);
a+=MemPageSize(a);
} while (a-dev.mem64_ptr<1<<30);
}
res=dev.mem64_ptr;
LBtr(&sys_semas[SYS_SEMA_DEV_MEM],0);
return res;
return dev.mem64_ptr;
}
U0 Mem64DevFree(U8 *base,I64 pages2Meg)
U0 Mem64DevFree(U8 *base,I64 pages1Gig)
{//Free 64-bit device address space.
if (!base) return;
while (LBts(&sys_semas[SYS_SEMA_DEV_MEM],0))
Yield;
if (base==dev.mem64_ptr)
dev.mem64_ptr+=pages2Meg*0x200000;
dev.mem64_ptr+=pages1Gig*1<<30;
//else not freed
LBtr(&sys_semas[SYS_SEMA_DEV_MEM],0);
}
U8 *MemVGAAlloc()
U0 UncachedAliasAlloc() //Make uncached alias for 4 lowest Gig.
{
I64 i=1,*a=Mem64DevAlloc(&i),*pte=MemPageTable(a);
*pte=0x197;
InvlPg(a);
return a;
I64 i=4,*pte;
U8 *a;
a=dev.uncached_alias=Mem64DevAlloc(&i);
do {
pte=MemPageTable(a);
*pte=0x197+a-dev.uncached_alias;
InvlPg(a);
a+=MemPageSize(a);
} while (a-dev.uncached_alias<1<<32);
}
I64 BIOSTotalMem()
@@ -191,4 +201,4 @@ I64 Scale2Mem(I64 min,I64 max,I64 limit=2*1024*1024*1024)
return max;
else
return min+(max-min)*i/limit;
}
}
Kernel/Mem/PageTables.CPP
+56 -36
View File
@@ -7,37 +7,59 @@ SYS_INIT_PAGE_TABLES::
MOV EDI,SYS_FIXED_AREA
XOR EAX,EAX
MOV ECX,sizeof(CSysFixedArea)/4
REP_STOSD //Init entire SYS_FIXED_AREA to zero
REP_STOSD //Init entire SYS_FIXED_AREA to zero
//PML2
MOV EAX,0x87 //bit 7 is page size (1==2Meg)
MOV EAX,0x80000001
CPUID
BT EDX,26
JC @@15
MOV U8 [SYS_GIG_PAGES],FALSE
//PML2: Use 2Meg PAges
MOV EAX,0x87 //bit 7 is page size (2Meg)
XOR EDX,EDX
MOV EDI,SYS_FIXED_AREA+CSysFixedArea.pml2
MOV ECX,MEM_NUM_PML2*0x200
@@20: MOV U32 [EDI],EAX
MOV ECX,MEM_NUM_2MEG
@@05: MOV U32 [EDI],EAX
ADD EDI,4
MOV U32 [EDI],EDX
ADD EDI,4
ADD EAX,0x200000
ADC EDX,0
LOOP @@20
//0xE0000000-0xFFFFFFFF: PCI Devs
MOV EAX,0x17 //Cache disabled
XOR EDX,EDX
MOV EDI,SYS_FIXED_AREA+CSysFixedArea.pml2+8*0x700
MOV ECX,0x800-0x700
@@25: OR U32 [EDI],EAX
ADD EDI,4
OR U32 [EDI],EDX
ADD EDI,4
LOOP @@25
//PML3
LOOP @@05
//PML3: Use 2Meg Pages
MOV EAX,SYS_FIXED_AREA+CSysFixedArea.pml2+7
XOR EDX,EDX
MOV EDI,SYS_FIXED_AREA+CSysFixedArea.pml3
MOV ECX,MEM_NUM_PML2
MOV ECX,MEM_NUM_USED_1GIG
@@10: MOV U32 [EDI],EAX
ADD EDI,4
MOV U32 [EDI],EDX
ADD EDI,4
ADD EAX,0x1000
ADC EDX,0
LOOP @@10
JMP @@25
@@15: MOV U8 [SYS_GIG_PAGES],TRUE
//PML3: Use 1Gig Pages
MOV EAX,0x87 //bit 7 is page size (1Gig)
XOR EDX,EDX
MOV EDI,SYS_FIXED_AREA+CSysFixedArea.pml3
MOV ECX,MEM_NUM_USED_1GIG
@@20: MOV U32 [EDI],EAX
ADD EDI,4
MOV U32 [EDI],EDX
ADD EDI,4
ADD EAX,0x40000000
ADC EDX,0
LOOP @@20
//PML4
@@25: MOV EAX,SYS_FIXED_AREA+CSysFixedArea.pml3+7
XOR EDX,EDX
MOV EDI,SYS_FIXED_AREA+CSysFixedArea.pml4
MOV ECX,MEM_NUM_1GIG/(0x1000/8)
@@30: MOV U32 [EDI],EAX
ADD EDI,4
MOV U32 [EDI],EDX
@@ -46,19 +68,6 @@ SYS_INIT_PAGE_TABLES::
ADC EDX,0
LOOP @@30
//PML4
MOV EAX,SYS_FIXED_AREA+CSysFixedArea.pml3+7
XOR EDX,EDX
MOV EDI,SYS_FIXED_AREA+CSysFixedArea.pml4
MOV ECX,MEM_NUM_PML3
@@35: MOV U32 [EDI],EAX
ADD EDI,4
MOV U32 [EDI],EDX
ADD EDI,4
ADD EAX,0x1000
ADC EDX,0
LOOP @@35
MOV U32 [SYS_CODE_BP],SYS_FIXED_AREA+CSysFixedArea.adam_bp
MOV U32 [SYS_CODE_BP+4],0
@@ -93,7 +102,7 @@ pain without MAlloc up-and-running.
//EBX=BASE EAX=SIZE
TEST U8 [SYS_MEM_INIT_FLAG],1
JZ @@40
JZ @@35
PUSH EAX
MOV EDI,EBX
MOV ECX,EAX
@@ -101,7 +110,7 @@ pain without MAlloc up-and-running.
REP_STOSB
POP EAX
@@40: SHR EAX,MEM_PAGE_BITS
@@35: SHR EAX,MEM_PAGE_BITS
MOV ESI,SYS_FIXED_AREA+CSysFixedArea.adam_bp
MOV EDI,U32 CBlkPool.mem_free_lst[ESI]
MOV U32 CMemBlk.next[EBX],EDI
@@ -117,7 +126,18 @@ pain without MAlloc up-and-running.
I64 *MemPageTable(U8 *a)
{//Point to page table entry for addr.
return SYS_FIXED_AREA+offset(CSysFixedArea.pml2)+a>>21*8;
if (sys_gig_pages)
return SYS_FIXED_AREA+offset(CSysFixedArea.pml3)+a>>30*8;
else
return SYS_FIXED_AREA+offset(CSysFixedArea.pml2)+a>>21*8;
}
I64 MemPageSize(U8 *)
{//Page table entry size for addr.
if (sys_gig_pages)
return 1<<30; //1Gig
else
return 1<<21; //2Meg
}
Bool MemPagePresentMark(U8 *a,Bool val)