TempleOSCDV3.11.ISO
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Terry A. Davis authored and minexew committed
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@@ -1,21 +1,23 @@
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/* See $LK,"AsmHashLoad",A="MN:AsmHashLoad"$().
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'!'= don't switch modes
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'&'= default
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'%'= Not allowed in 64-bit mode
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'='= Rex 0x48 only if 64-bit mode
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'`'= Rex only R8-R15
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'^'= Rex xor-like
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':'= floating sti-like for disassembly
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'$$'= ending zero (ENTER)
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$FG,4$Note:$FG$ TempleOS uses nonstandard opcodes.
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Asm is kind-of a bonus and I made changes
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to make the assembler simpler. For opcodes
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which can have different numbers of
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args, I separated them out -- Like IMUL and IMUL2.
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The assembler will not report certain invalid
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forms. Get an Intel datasheet and learn
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which forms are valid.
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'!'= IEF_DONT_SWITCH_MODES
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'&'= IEF_DFT
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'%'= IEF_NOT_IN_64_BIT Not Allowed in 64-bit.
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'='= IEF_48_REX Rex 0x48 only if in 64-bit mode.
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'`'= IEF_REX_ONLY_R8_R15
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'^'= IEF_REX_XOR_LIKE
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'*'= IEF_STI_LIKE Floating STI-like for UAsm.
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'$$'= IEF_ENDING_ZERO Ending zero for ENTER.
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$FG,4$Note:$FG$ TempleOS uses nonstandard opcodes.
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Asm is kind-of a bonus and I made changes
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to make the assembler simpler. For opcodes
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which can have different numbers of
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args, I separated them out -- Like IMUL and IMUL2.
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The assembler will not report certain invalid
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forms. Get an Intel datasheet and learn
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which forms are valid.
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*/
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R8 AL 0;
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@@ -1296,15 +1298,15 @@ OPCODE FISTTP
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OPCODE FLD
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0xD9,/0 M32 //Load F32
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0xDD,/0 ` M64 //Load F64
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0xD9 0xC0,+I: STI;
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0xD9 0xC0,+I* STI;
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OPCODE FSTP
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0xD9,/3 M32 //Store F32
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0xDD,/3 ` M64 //Store F64
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0xDD 0xD8,+I: STI;
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0xDD 0xD8,+I* STI;
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OPCODE FST
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0xD9,/2 M32 //Store F32
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0xDD,/2 ` M64 //Store F64
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0xDD 0xD0,+I: STI;
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0xDD 0xD0,+I* STI;
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OPCODE FRSTOR
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0xDD,/4 M32
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0xDD,/4 M64;
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@@ -1312,79 +1314,79 @@ OPCODE FSAVE
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0xDD,/6 M32
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0xDD,/6 M64;
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OPCODE FYL2X 0xD9 0xF1,:;
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OPCODE FYL2XP1 0xD9 0xF9,:;
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OPCODE F2XM1 0xD9 0xF0,:;
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OPCODE FABS 0xD9 0xE1,:;
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OPCODE FCHS 0xD9 0xE0,:;
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OPCODE FSIN 0xD9 0xFE,:;
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OPCODE FCOS 0xD9 0xFF,:;
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OPCODE FPTAN 0xD9 0xF2,:;
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OPCODE FPATAN 0xD9 0xF3,:;
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OPCODE FSQRT 0xD9 0xFA,:;
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OPCODE FMULP 0xDE 0xC8,+I: STI ST0;
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OPCODE FYL2X 0xD9 0xF1,*;
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OPCODE FYL2XP1 0xD9 0xF9,*;
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OPCODE F2XM1 0xD9 0xF0,*;
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OPCODE FABS 0xD9 0xE1,*;
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OPCODE FCHS 0xD9 0xE0,*;
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OPCODE FSIN 0xD9 0xFE,*;
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OPCODE FCOS 0xD9 0xFF,*;
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OPCODE FPTAN 0xD9 0xF2,*;
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OPCODE FPATAN 0xD9 0xF3,*;
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OPCODE FSQRT 0xD9 0xFA,*;
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OPCODE FMULP 0xDE 0xC8,+I* STI ST0;
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OPCODE FMUL
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0xD8,/1 ST0 M32
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0xDC,/1 ` ST0 M64
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0xD8 0xC8,+I: ST0 STI
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0xDC 0xC8,+I: STI ST0;
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0xD8 0xC8,+I* ST0 STI
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0xDC 0xC8,+I* STI ST0;
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OPCODE FIMUL
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0xDA,/1 ST0 M32
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0xDE,/1 ST0 M16;
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OPCODE FDIVP 0xDE 0xF8,+I: STI ST0;
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OPCODE FDIVP 0xDE 0xF8,+I* STI ST0;
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OPCODE FDIV
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0xD8,/6 ST0 M32
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0xDC,/6 ` ST0 M64
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0xD8 0xF0,+I: ST0 STI
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0xDC 0xF8,+I: STI ST0;
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OPCODE FDIVRP 0xDE 0xF0,+I: STI ST0;
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0xD8 0xF0,+I* ST0 STI
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0xDC 0xF8,+I* STI ST0;
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OPCODE FDIVRP 0xDE 0xF0,+I* STI ST0;
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OPCODE FDIVR
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0xD8,/7 ST0 M32
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0xDC,/7 ` ST0 M64
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0xD8 0xF8,+I: ST0 STI
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0xDC 0xF0,+I: STI ST0;
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OPCODE FPREM 0xD9 0xF8,:;
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OPCODE FADDP 0xDE 0xC0,+I: STI ST0;
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0xD8 0xF8,+I* ST0 STI
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0xDC 0xF0,+I* STI ST0;
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OPCODE FPREM 0xD9 0xF8,*;
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OPCODE FADDP 0xDE 0xC0,+I* STI ST0;
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OPCODE FADD
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0xD8,/0 ST0 M32
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0xDC,/0 ` ST0 M64
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0xD8 0xC0,+I: ST0 STI
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0xDC 0xC0,+I: STI ST0;
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OPCODE FSUBP 0xDE 0xE8,+I: STI ST0;
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0xD8 0xC0,+I* ST0 STI
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0xDC 0xC0,+I* STI ST0;
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OPCODE FSUBP 0xDE 0xE8,+I* STI ST0;
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OPCODE FSUB
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0xD8,/4 ST0 M32
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0xDC,/4 ` ST0 M64
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0xD8 0xE0,+I: ST0 STI
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0xDC 0xE8,+I: STI ST0;
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OPCODE FSUBRP 0xDE 0xE0,+I: STI ST0;
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0xD8 0xE0,+I* ST0 STI
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0xDC 0xE8,+I* STI ST0;
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OPCODE FSUBRP 0xDE 0xE0,+I* STI ST0;
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OPCODE FSUBR
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0xD8,/5 ST0 M32
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0xDC,/5 ` ST0 M64
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0xD8 0xE8,+I: ST0 STI
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0xDC 0xE0,+I: STI ST0;
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OPCODE FCOMIP 0xDF 0xF0,+I: ST0 STI;
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OPCODE FCOMI 0xDB 0xF0,+I: ST0 STI;
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OPCODE FCLEX 0x9B 0xDB 0xE2,:;
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OPCODE FNCLEX 0xDB 0xE2,:;
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OPCODE FSTSW 0xDF 0xE0,:;
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OPCODE FDECSTP 0xD9 0xF6,:;
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OPCODE FINCSTP 0xD9 0xF7,:;
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OPCODE FFREE 0xDD 0xC0,+I: STI;
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OPCODE FRNDINT 0xD9 0xFC,:;
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OPCODE FSCALE 0xD9 0xFD,:;
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OPCODE FXTRACT 0xD9 0xF4,:;
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0xD8 0xE8,+I* ST0 STI
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0xDC 0xE0,+I* STI ST0;
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OPCODE FCOMIP 0xDF 0xF0,+I* ST0 STI;
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OPCODE FCOMI 0xDB 0xF0,+I* ST0 STI;
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OPCODE FCLEX 0x9B 0xDB 0xE2,*;
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OPCODE FNCLEX 0xDB 0xE2,*;
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OPCODE FSTSW 0xDF 0xE0,*;
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OPCODE FDECSTP 0xD9 0xF6,*;
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OPCODE FINCSTP 0xD9 0xF7,*;
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OPCODE FFREE 0xDD 0xC0,+I* STI;
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OPCODE FRNDINT 0xD9 0xFC,*;
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OPCODE FSCALE 0xD9 0xFD,*;
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OPCODE FXTRACT 0xD9 0xF4,*;
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OPCODE FLD1 0xD9 0xE8,:;
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OPCODE FLDL2T 0xD9 0xE9,:;
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OPCODE FLDL2E 0xD9 0xEA,:;
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OPCODE FLDPI 0xD9 0xEB,:;
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OPCODE FLDLG2 0xD9 0xEC,:;
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OPCODE FLDLN2 0xD9 0xED,:;
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OPCODE FLDZ 0xD9 0xEE,:;
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OPCODE FLD1 0xD9 0xE8,*;
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OPCODE FLDL2T 0xD9 0xE9,*;
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OPCODE FLDL2E 0xD9 0xEA,*;
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OPCODE FLDPI 0xD9 0xEB,*;
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OPCODE FLDLG2 0xD9 0xEC,*;
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OPCODE FLDLN2 0xD9 0xED,*;
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OPCODE FLDZ 0xD9 0xEE,*;
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OPCODE FXCH 0xD9 0xC8,+I: STI;
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OPCODE FTST 0xD9 0xE4,:;
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OPCODE FXAM 0xD9 0xE5,:;
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OPCODE FXCH 0xD9 0xC8,+I* STI;
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OPCODE FTST 0xD9 0xE4,*;
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OPCODE FXAM 0xD9 0xE5,*;
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OPCODE FINIT 0x9B 0xDB 0xE3;
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OPCODE FNINIT 0xDB 0xE3;
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