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TempleOSCDV5.00.ISO

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Terry A. Davis authored and minexew committed 2018-09-08 21:48:09 +02:00
1 parent 122df6338e
commit f6eacf7744
374 files changed
+11078 -11204
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Kernel/Mem/MemPhysical.HC
+16 -39
View File
@@ -30,7 +30,7 @@ Bool Mem32DevIns(CMemRange *tmpmr)
U0 Mem32DevInit()
{
CMemRange *tmpmr;
CMemE820 *m20=SYS_MEM_E820;
CMemE820 *m20=MEM_E820;
QueInit(&dev.mem32_head);
tmpmr=AMAlloc(sizeof(CMemRange));
@@ -55,36 +55,13 @@ U0 Mem32DevInit()
}
}
U0 MemPagesNotPresentMark()
{
U8 *a,*max_physical=NULL;
U16 *m01=SYS_MEM_E801;
CMemE820 *m20=SYS_MEM_E820;
while (m20->type) {
a=m20->base+m20->len;
if (a>max_physical)
max_physical=a;
m20++;
}
if (max_physical>=0x1000000+m01[1]<<16) {
if (sys_gig_pages)
a=(max_physical+0x3FFFFFFF)&~0x3FFFFFFF;
else
a=(max_physical+0x1FFFFF)&~0x1FFFFF;
while (a<MEM_MAPPED_SPACE) {
MemPagePresentMark(a,FALSE);
a+=MemPageSize(a);
}
}
}
U8 *Mem32DevAlloc(I64 size,I64 alignment)
{//Alloc 32-bit addr space for device. (Doesn't work.) Not used.
//For this to work the BIOS E820 map must be searched for gaps in
//the 32-bit range and the pool initialized to the gaps.
U8 *base,*limit;
CMemRange *tmpmr,*tmpmr1;
while (LBts(&sys_semas[SYS_SEMA_DEV_MEM],0))
while (LBts(&sys_semas[SEMA_DEV_MEM],0))
Yield;
tmpmr1=dev.mem32_head.next;
while (tmpmr1!=&dev.mem32_head) {
@@ -99,15 +76,15 @@ U8 *Mem32DevAlloc(I64 size,I64 alignment)
tmpmr->size=size;
if (!Mem32DevIns(tmpmr)) {
Free(tmpmr);
LBtr(&sys_semas[SYS_SEMA_DEV_MEM],0);
LBtr(&sys_semas[SEMA_DEV_MEM],0);
return NULL;
}
LBtr(&sys_semas[SYS_SEMA_DEV_MEM],0);
LBtr(&sys_semas[SEMA_DEV_MEM],0);
return tmpmr->base;
}
tmpmr1=tmpmr1->next;
}
LBtr(&sys_semas[SYS_SEMA_DEV_MEM],0);
LBtr(&sys_semas[SEMA_DEV_MEM],0);
return NULL;
}
@@ -115,7 +92,7 @@ U0 Mem32DevFree(U8 *base)
{//Free 32-bit device address space.
CMemRange *tmpmr;
if (!base) return;
while (LBts(&sys_semas[SYS_SEMA_DEV_MEM],0))
while (LBts(&sys_semas[SEMA_DEV_MEM],0))
Yield;
tmpmr=dev.mem32_head.next;
while (tmpmr!=&dev.mem32_head) {
@@ -125,14 +102,14 @@ U0 Mem32DevFree(U8 *base)
}
tmpmr=tmpmr->next;
}
LBtr(&sys_semas[SYS_SEMA_DEV_MEM],0);
LBtr(&sys_semas[SEMA_DEV_MEM],0);
}
U8 *Mem64DevAlloc(I64 *_pages1Gig)
{//Alloc 64-bit addr space for device.
U8 *a;
I64 i=*_pages1Gig,*pte;
while (LBts(&sys_semas[SYS_SEMA_DEV_MEM],0))
while (LBts(&sys_semas[SEMA_DEV_MEM],0))
Yield;
while (i--) {
a=dev.mem64_ptr-=1<<30;
@@ -140,22 +117,22 @@ U8 *Mem64DevAlloc(I64 *_pages1Gig)
pte=MemPageTable(a);
*pte=*pte&~0x18 |0x11; //Uncached and present
InvlPg(dev.mem64_ptr);
a+=MemPageSize(a);
a+=mem_page_size;
} while (a-dev.mem64_ptr<1<<30);
}
LBtr(&sys_semas[SYS_SEMA_DEV_MEM],0);
LBtr(&sys_semas[SEMA_DEV_MEM],0);
return dev.mem64_ptr;
}
U0 Mem64DevFree(U8 *base,I64 pages1Gig)
{//Free 64-bit device address space.
if (!base) return;
while (LBts(&sys_semas[SYS_SEMA_DEV_MEM],0))
while (LBts(&sys_semas[SEMA_DEV_MEM],0))
Yield;
if (base==dev.mem64_ptr)
dev.mem64_ptr+=pages1Gig*1<<30;
//else not freed
LBtr(&sys_semas[SYS_SEMA_DEV_MEM],0);
LBtr(&sys_semas[SEMA_DEV_MEM],0);
}
U0 UncachedAliasAlloc() //Make uncached alias for 4 lowest Gig.
@@ -167,15 +144,15 @@ U0 UncachedAliasAlloc() //Make uncached alias for 4 lowest Gig.
pte=MemPageTable(a);
*pte=0x197+a-dev.uncached_alias;
InvlPg(a);
a+=MemPageSize(a);
a+=mem_page_size;
} while (a-dev.uncached_alias<1<<32);
}
I64 BIOSTotalMem()
{
I64 r01,r20;
U16 *m01=SYS_MEM_E801;
CMemE820 *m20=SYS_MEM_E820;
U16 *m01=MEM_E801;
CMemE820 *m20=MEM_E820;
r01=0x100000+m01[0]<<10+m01[1]<<16;
r20=0;
@@ -201,4 +178,4 @@ I64 Scale2Mem(I64 min,I64 max,I64 limit=2*1024*1024*1024)
return max;
else
return min+(max-min)*i/limit;
}
}