TempleOSCD_150720.ISO
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@@ -13,14 +13,13 @@ asm {
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//Opcodes are slightly different to make writing my x86_64 assembler easier.
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//See $LK,"::/Compiler/OpCodes.TXT"$.
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USE64 //Defaults to 64, but this is a good habit.
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JIFFIES_MSG: DU8 "Jiffies:",0;
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//See $LK,"::/Kernel/StrA.CPP",A="FL:::/Kernel/StrA.CPP,1"$ and $LK,"::/Kernel/KUtils.CPP"$.
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_BEEPS2::
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//You can clobber RAX,RBX,RCX,RDX,R8,R9. The compiler expects that.
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//See $LK,"REGG_C_CLOBBERED",A="MN:REGG_C_CLOBBERED"$ and $LK,"REGG_C_TEMP_CLOBBERED",A="MN:REGG_C_TEMP_CLOBBERED"$.
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PUSH RBP
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MOV RBP,RSP
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MOV RCX,U64 SF_ARG1[RBP] //$LK,"SF_ARG1",A="FF:::/Kernel/KernelA.HPP,SF_ARG1"$
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@@ -35,7 +34,7 @@ _BEEPS2::
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POP RCX
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LOOP @@05
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PUSH RSI //See $LK,"REG_VARS_MASK",A="MN:REG_VARS_MASK"$ & $LK,"REG_NON_PTR_MASK",A="MN:REG_NON_PTR_MASK"$
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PUSH RSI //See $LK,"REGG_C_LOCAL_VARS",A="MN:REGG_C_LOCAL_VARS"$ & $LK,"REGG_C_LOCAL_NON_PTR_VARS",A="MN:REGG_C_LOCAL_NON_PTR_VARS"$
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MOV RSI,JIFFIES_MSG
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CALL PUT_STR
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POP RSI
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@@ -63,30 +62,28 @@ U0 AsmAndC2()
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Beeps2(i);
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asm {
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LIST
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LIST
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//You can clobber RAX,RBX,RCX,RDX, but preserve the rest.
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USE64 //Defaults to 64, but this is a good habit.
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MOV RCX,R15 //You can clobber RAX,RBX,RCX,RDX. Preserve the rest.
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MOV RCX,R15 //You can clobber RAX,RBX,RCX,RDX. Preserve the rest.
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@@05: PUSH RCX
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@@05: PUSH RCX
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//U0 $LK,"Snd",A="MN:Snd"$(F64 freq);
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MOV RAX,RCX //freq=loop*100.0+100.0
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IMUL2 RAX,glbl_hz_step //evaluated at compile ttime
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ADD RAX,U64 [&glbl_hz_base] //evaluated at run time
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PUSH RAX
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FILD U64 [RSP] //Convert from int to floating
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FSTP U64 [RSP]
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MOV RAX,RCX //freq=loop*100.0+100.0
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IMUL2 RAX,glbl_hz_step //evaluated at compile ttime
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ADD RAX,U64 [&glbl_hz_base] //evaluated at run time
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PUSH RAX
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FILD U64 [RSP] //Convert from int to floating
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FSTP U64 [RSP]
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CALL &Snd //We can skip IMPORT with & if JIT compiling.
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CALL &Snd //We can skip IMPORT with & if JIT compiling.
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MOV RCX,cnts.time_stamp_freq>>3 //JIT Const. Simple delay loop.
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MOV RCX,cnts.time_stamp_freq>>3 //JIT Const. Simple delay loop.
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@@10: LOOP @@10
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POP RCX
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LOOP @@05
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POP RCX
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LOOP @@05
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}
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Snd(0);
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}
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