4084 lines
66 KiB
Plaintext
4084 lines
66 KiB
Plaintext
ALIGN 8,0x90
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FAR_AWAY: //(FOR DUMMY U4 JMPS)
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ALIGN 4
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INTERNAL_TYPES_TABLE::
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DU4 HTT_INTERNAL_TYPE,IT_I4,4;
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DU1 "void",0;
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DU4 HTT_INTERNAL_TYPE,IT_DOUBLE,8;
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DU1 "double",0;
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DU4 HTT_INTERNAL_TYPE,IT_I0,0;
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DU1 "I0i",0;
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DU4 HTT_INTERNAL_TYPE,IT_U0,0;
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DU1 "U0i",0;
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DU4 HTT_INTERNAL_TYPE,IT_I0,0;
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DU1 "I0",0;
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DU4 HTT_INTERNAL_TYPE,IT_U0,0;
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DU1 "U0",0;
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DU4 HTT_INTERNAL_TYPE,IT_I1,1;
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DU1 "I1i",0;
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DU4 HTT_INTERNAL_TYPE,IT_U1,1;
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DU1 "U1i",0;
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DU4 HTT_INTERNAL_TYPE,IT_I1,1;
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DU1 "I1",0;
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DU4 HTT_INTERNAL_TYPE,IT_U1,1;
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DU1 "U1",0;
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DU4 HTT_INTERNAL_TYPE,IT_I2,2;
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DU1 "I2i",0;
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DU4 HTT_INTERNAL_TYPE,IT_U2,2;
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DU1 "U2i",0;
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DU4 HTT_INTERNAL_TYPE,IT_I4,4;
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DU1 "I4i",0;
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DU4 HTT_INTERNAL_TYPE,IT_U4,4;
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DU1 "U4i",0;
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DU4 HTT_INTERNAL_TYPE,IT_I8,8;
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DU1 "I8i",0;
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DU4 HTT_INTERNAL_TYPE,IT_U8,8;
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DU1 "U8i",0;
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DU4 HTT_INVALID;
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//*******************************************************
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ALIGN 8,0x90
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I_OPT_NOP:
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DU4 EC_NOP; //Must be at IC_CODE offset
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/**********
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void OptNext(IntermediateCode *tempi,
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IntermediateCode **temp_lag)
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{
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I8 i,j=0;
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for (i=3;i>0;i--)
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temp_lag[i]=temp_lag[i-1];
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temp_lag[0]=tempi;
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for (i=0;i<4;i++) //TODO: move end_exp
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if (temp_lag[i]->ic_code.u2[0]>EC_END_EXP)
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temp_lag[j++]=temp_lag[i];
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while (j<4)
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temp_lag[j++]=&opt_nop;
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}
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************/
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ALIGN 8,0x90
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CP_OPTNEXT::
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PUSH EBP
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MOV EBP,ESP
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PUSH EDI
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MOV ECX,U4 SF_PARAM1[EBP]
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MOV EDX,U4 SF_PARAM2[EBP]
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MOV EAX,U4 8[EDX]
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MOV U4 12[EDX],EAX
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MOV EAX,U4 4[EDX]
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MOV U4 8[EDX],EAX
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MOV EAX,U4 [EDX]
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MOV U4 4[EDX],EAX
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MOV U4 [EDX],ECX
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MOV EDI,EDX
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MOV EAX,U4 [EDX]
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CMP U2 IC_CODE[EAX],EC_END_EXP
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JBE @@10
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STOSD
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@@10: MOV EAX,U4 4[EDX]
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CMP U2 IC_CODE[EAX],EC_END_EXP
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JBE @@11
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STOSD
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@@11: MOV EAX,U4 8[EDX]
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CMP U2 IC_CODE[EAX],EC_END_EXP
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JBE @@12
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STOSD
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@@12: MOV EAX,U4 12[EDX]
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CMP U2 IC_CODE[EAX],EC_END_EXP
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JBE @@13
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STOSD
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@@13: MOV EAX,I_OPT_NOP
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ADD EDX,16
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JMP @@15
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@@14: STOSD
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@@15: CMP EDI,EDX
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JB @@14
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@@100: MOV EAX,1
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XOR EDX,EDX
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POP EDI
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POP EBP
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RET
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//*******************************************************
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/****
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void PrsPush(ParseStack *ps,U4 val)
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{
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ps->stk[ps->ptr++]=val;
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}
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U8 PrsPop(ParseStack *ps)
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{
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return ps->stk[--ps->ptr];
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}
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******/
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ALIGN 8,0x90
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CP_PRSPUSH::
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PUSH EBP
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MOV EBP,ESP
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MOV ECX,U4 SF_PARAM1[EBP]
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MOV EAX,U4 [ECX]
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LEA EBX,U4 4[ECX+EAX*4]
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INC EAX
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MOV EDX,U4 SF_PARAM2[EBP]
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MOV U4 [ECX],EAX
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MOV U4 [EBX],EDX
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POP EBP
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RET
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ALIGN 8,0x90
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CP_PRSPOP::
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PUSH EBP
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MOV EBP,ESP
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MOV ECX,U4 SF_PARAM1[EBP]
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MOV EAX,U4 [ECX]
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DEC EAX
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MOV U4 [ECX],EAX
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MOV EAX,U4 4[ECX+EAX*4]
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XOR EDX,EDX
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POP EBP
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RET
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//*******************************************************
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ALIGN 8,0x90
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CODE_TABLE::
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DU4 ICT_NULL;
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DU4 ICT_NOP;
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DU4 ICT_END_EXP;
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DU4 ICT_ZERO;
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DU4 ICT_U8;
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DU4 ICT_U4;
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DU4 ICT_U2;
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DU4 ICT_U1;
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DU4 ICT_DOUBLE;
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DU4 ICT_STRING_CONSTANT;
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DU4 ICT_EBP;
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DU4 ICT_FS;
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DU4 ICT_ESI;
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DU4 ICT_EDI;
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DU4 ICT_TO_DOUBLE;
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DU4 ICT_TO_INT;
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DU4 ICT_COM;
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DU4 ICT_NOT;
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DU4 ICT_UNARY_MINUS;
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DU4 ICT_ADDRESS;
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DU4 ICT_U8_DISP32;
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DU4 ICT_U4_DISP32;
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DU4 ICT_U2_DISP32;
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DU4 ICT_U1_DISP32;
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DU4 ICT_U8_DISP8;
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DU4 ICT_U4_DISP8;
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DU4 ICT_U2_DISP8;
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DU4 ICT_U1_DISP8;
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DU4 ICT_FS_U8_DISP32;
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DU4 ICT_FS_U4_DISP32;
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DU4 ICT_FS_U2_DISP32;
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DU4 ICT_FS_U1_DISP32;
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DU4 ICT_ESI_U8_DISP32;
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DU4 ICT_ESI_U4_DISP32;
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DU4 ICT_ESI_U2_DISP32;
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DU4 ICT_ESI_U1_DISP32;
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DU4 ICT_ESI_U8_DISP8;
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DU4 ICT_ESI_U4_DISP8;
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DU4 ICT_ESI_U2_DISP8;
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DU4 ICT_ESI_U1_DISP8;
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DU4 ICT_EDI_U8_DISP32;
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DU4 ICT_EDI_U4_DISP32;
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DU4 ICT_EDI_U2_DISP32;
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DU4 ICT_EDI_U1_DISP32;
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DU4 ICT_EDI_U8_DISP8;
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DU4 ICT_EDI_U4_DISP8;
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DU4 ICT_EDI_U2_DISP8;
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DU4 ICT_EDI_U1_DISP8;
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DU4 ICT_DEREF_U8;
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DU4 ICT_DEREF_U4;
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DU4 ICT_DEREF_U2;
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DU4 ICT_DEREF_U1;
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DU4 ICT_ESI_DEREF_U8;
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DU4 ICT_ESI_DEREF_U4;
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DU4 ICT_ESI_DEREF_U2;
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DU4 ICT_ESI_DEREF_U1;
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DU4 ICT_EDI_DEREF_U8;
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DU4 ICT_EDI_DEREF_U4;
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DU4 ICT_EDI_DEREF_U2;
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DU4 ICT_EDI_DEREF_U1;
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DU4 ICT_U8_PP;
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DU4 ICT_U4_PP;
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DU4 ICT_U2_PP;
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DU4 ICT_U1_PP;
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DU4 ICT_U8_MM;
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DU4 ICT_U4_MM;
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DU4 ICT_U2_MM;
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DU4 ICT_U1_MM;
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DU4 ICT_PP_U8;
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DU4 ICT_PP_U4;
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DU4 ICT_PP_U2;
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DU4 ICT_PP_U1;
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DU4 ICT_MM_U8;
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DU4 ICT_MM_U4;
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DU4 ICT_MM_U2;
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DU4 ICT_MM_U1;
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DU4 ICT_ESI_U4_PP;
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DU4 ICT_ESI_U4_MM;
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DU4 ICT_ESI_PP_U4;
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DU4 ICT_ESI_MM_U4;
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DU4 ICT_EDI_U4_PP;
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DU4 ICT_EDI_U4_MM;
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DU4 ICT_EDI_PP_U4;
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DU4 ICT_EDI_MM_U4;
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DU4 ICT_LEA_DISP32_EBP;
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DU4 ICT_LEA_DISP8_EBP;
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DU4 ICT_U8_DISP32_SCALED;
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DU4 ICT_U4_DISP32_SCALED;
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DU4 ICT_U2_DISP32_SCALED;
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DU4 ICT_SHL;
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DU4 ICT_SHR;
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DU4 ICT_SHL_CONSTANT1;
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DU4 ICT_SHL_CONSTANT2;
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DU4 ICT_SHR_CONSTANT1;
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DU4 ICT_SHR_CONSTANT2;
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DU4 ICT_POWER;
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DU4 ICT_MULTIPLICATION;
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DU4 ICT_DIVISION;
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DU4 ICT_REMAINDER;
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DU4 ICT_AND;
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DU4 ICT_OR;
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DU4 ICT_XOR;
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DU4 ICT_ADDITION;
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DU4 ICT_SUBTRACTION;
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DU4 ICT_EQUAL_EQUAL;
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DU4 ICT_NOT_EQUAL_TO;
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DU4 ICT_LESS_THAN;
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DU4 ICT_GREATER_THAN;
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DU4 ICT_LESS_OR_EQUAL;
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DU4 ICT_GREATER_OR_EQUAL;
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DU4 ICT_AND_AND;
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DU4 ICT_OR_OR;
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DU4 ICT_XOR_XOR;
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DU4 ICT_COLON;
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DU4 ICT_QUESTION;
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DU4 ICT_ASSIGN_U8;
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DU4 ICT_ASSIGN_U4;
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DU4 ICT_ASSIGN_U2;
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DU4 ICT_ASSIGN_U1;
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DU4 ICT_SHL_EQUAL_U8;
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DU4 ICT_SHL_EQUAL_U4;
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DU4 ICT_SHL_EQUAL_U2;
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DU4 ICT_SHL_EQUAL_U1;
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DU4 ICT_SHR_EQUAL_U8;
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DU4 ICT_SHR_EQUAL_U4;
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DU4 ICT_SHR_EQUAL_U2;
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DU4 ICT_SHR_EQUAL_U1;
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DU4 ICT_MUL_EQUAL_U8;
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DU4 ICT_MUL_EQUAL_U4;
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DU4 ICT_MUL_EQUAL_U2;
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DU4 ICT_MUL_EQUAL_U1;
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DU4 ICT_DIV_EQUAL_U8;
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DU4 ICT_DIV_EQUAL_U4;
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DU4 ICT_DIV_EQUAL_U2;
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DU4 ICT_DIV_EQUAL_U1;
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DU4 ICT_AND_EQUAL_U8;
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DU4 ICT_AND_EQUAL_U4;
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DU4 ICT_AND_EQUAL_U2;
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DU4 ICT_AND_EQUAL_U1;
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DU4 ICT_OR_EQUAL_U8;
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DU4 ICT_OR_EQUAL_U4;
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DU4 ICT_OR_EQUAL_U2;
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DU4 ICT_OR_EQUAL_U1;
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DU4 ICT_XOR_EQUAL_U8;
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DU4 ICT_XOR_EQUAL_U4;
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DU4 ICT_XOR_EQUAL_U2;
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DU4 ICT_XOR_EQUAL_U1;
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DU4 ICT_ADD_EQUAL_U8;
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DU4 ICT_ADD_EQUAL_U4;
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DU4 ICT_ADD_EQUAL_U2;
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DU4 ICT_ADD_EQUAL_U1;
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DU4 ICT_SUB_EQUAL_U8;
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DU4 ICT_SUB_EQUAL_U4;
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DU4 ICT_SUB_EQUAL_U2;
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DU4 ICT_SUB_EQUAL_U1;
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DU4 ICT_ESI_ASSIGN_U4;
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DU4 ICT_ESI_SHL_EQUAL_U4;
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DU4 ICT_ESI_SHR_EQUAL_U4;
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DU4 ICT_ESI_MUL_EQUAL_U4;
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DU4 ICT_ESI_DIV_EQUAL_U4;
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DU4 ICT_ESI_AND_EQUAL_U4;
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DU4 ICT_ESI_OR_EQUAL_U4;
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DU4 ICT_ESI_XOR_EQUAL_U4;
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DU4 ICT_ESI_ADD_EQUAL_U4;
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DU4 ICT_ESI_SUB_EQUAL_U4;
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DU4 ICT_EDI_ASSIGN_U4;
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DU4 ICT_EDI_SHL_EQUAL_U4;
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DU4 ICT_EDI_SHR_EQUAL_U4;
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DU4 ICT_EDI_MUL_EQUAL_U4;
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DU4 ICT_EDI_DIV_EQUAL_U4;
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DU4 ICT_EDI_AND_EQUAL_U4;
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DU4 ICT_EDI_OR_EQUAL_U4;
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DU4 ICT_EDI_XOR_EQUAL_U4;
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DU4 ICT_EDI_ADD_EQUAL_U4;
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DU4 ICT_EDI_SUB_EQUAL_U4;
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DU4 ICT_ADD64;
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DU4 ICT_ADD32;
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DU4 ICT_ADD8;
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DU4 ICT_INC;
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DU4 ICT_SUB64;
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DU4 ICT_SUB32;
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DU4 ICT_SUB8;
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DU4 ICT_DEC;
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DU4 ICT_ENTER;
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DU4 ICT_LEAVE;
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DU4 ICT_ENTER1;
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DU4 ICT_LEAVE1;
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DU4 ICT_ENTER2;
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DU4 ICT_LEAVE2;
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DU4 ICT_ADD_ESP32;
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DU4 ICT_ADD_ESP8;
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DU4 ICT_RET;
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DU4 ICT_CALL;
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DU4 ICT_CALL_INDIRECT;
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DU4 ICT_CALL_INDIRECT2;
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DU4 ICT_IRQ;
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DU4 ICT_CLI;
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DU4 ICT_STI;
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DU4 ICT_GET_FLAGS;
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DU4 ICT_SET_FLAGS;
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DU4 ICT_GET_BASE_PTR;
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DU4 ICT_SET_BASE_PTR;
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DU4 ICT_GET_STACK_PTR;
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DU4 ICT_SET_STACK_PTR;
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DU4 ICT_GET_LABEL;
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DU4 ICT_ABSOLUTE_ADDRESS;
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DU4 ICT_LABEL;
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DU4 ICT_TYPE;
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DU4 ICT_BT;
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DU4 ICT_BTS;
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DU4 ICT_BTR;
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DU4 ICT_BTC;
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DU4 ICT_BSF;
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DU4 ICT_BSR;
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DU4 ICT_INSQUE;
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DU4 ICT_INSQUE_REV;
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DU4 ICT_REMQUE;
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DU4 ICT_STRLEN;
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DU4 ICT_MEMCPY;
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DU4 ICT_MEMSET;
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DU4 ICT_INPD;
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DU4 ICT_INPW;
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DU4 ICT_INP;
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DU4 ICT_OUTPD;
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DU4 ICT_OUTPW;
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DU4 ICT_OUTP;
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DU4 ICT_JMP;
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DU4 ICT_SHORT_JMP;
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DU4 ICT_SWITCH;
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DU4 ICT_SKIPZ;
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DU4 ICT_SKIPZ2;
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DU4 ICT_SKIPNZ;
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DU4 ICT_SKIPNZ2;
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DU4 ICT_EQUAL_EQUAL_SKIPZ;
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DU4 ICT_EQUAL_EQUAL_SKIPZ2;
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DU4 ICT_NOT_EQUAL_TO_SKIPZ;
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DU4 ICT_NOT_EQUAL_TO_SKIPZ2;
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DU4 ICT_LESS_THAN_SKIPZ;
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DU4 ICT_LESS_THAN_SKIPZ2;
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DU4 ICT_GREATER_THAN_SKIPZ;
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DU4 ICT_GREATER_THAN_SKIPZ2;
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DU4 ICT_LESS_OR_EQUAL_SKIPZ;
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DU4 ICT_LESS_OR_EQUAL_SKIPZ2;
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DU4 ICT_GREATER_OR_EQUAL_SKIPZ;
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DU4 ICT_GREATER_OR_EQUAL_SKIPZ2;
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DU4 ICT_AND_AND_SKIPZ;
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DU4 ICT_AND_AND_SKIPZ2;
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DU4 ICT_AND_AND_SKIPNZ;
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DU4 ICT_AND_AND_SKIPNZ2;
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DU4 ICT_OR_OR_SKIPZ;
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DU4 ICT_OR_OR_SKIPZ2;
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DU4 ICT_OR_OR_SKIPNZ;
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DU4 ICT_OR_OR_SKIPNZ2;
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DU4 ICT_LEA_DISP32_ESI;
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DU4 ICT_LEA_DISP8_ESI;
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DU4 ICT_LEA_DISP32_EDI;
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DU4 ICT_LEA_DISP8_EDI;
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DU4 ICT_PUSH_U8;
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DU4 ICT_PUSH_U4;
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DU4 ICT_PUSH_U2;
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DU4 ICT_PUSH_U1;
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DU4 ICT_PUSH_NEG_U4;
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DU4 ICT_PUSH_NEG_U2;
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DU4 ICT_PUSH_NEG_U1;
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DU4 ICT_PUSH_DOUBLE;
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DU4 ICT_PUSH_U8_DISP32;
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DU4 ICT_PUSH_U8_DISP8;
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DU4 ICT_PUSH_ESI_U8_DISP32;
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DU4 ICT_PUSH_ESI_U8_DISP8;
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DU4 ICT_PUSH_EDI_U8_DISP32;
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DU4 ICT_PUSH_EDI_U8_DISP8;
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DU4 ICT_PUSH_DEREF_U8;
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DU4 ICT_PUSH_U8_DISP32_SCALED;
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DU4 ICT_BT_CONSTANT;
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DU4 ICT_BTS_CONSTANT;
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DU4 ICT_BTR_CONSTANT;
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DU4 ICT_BTC_CONSTANT;
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DU4 ICT_ESI_NEXT_EQUAL_U4;
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DU4 ICT_EDI_NEXT_EQUAL_U4;
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DU4 ICT_ADD_EQUAL_U8_CONSTANT_U1;
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DU4 ICT_SUB_EQUAL_U8_CONSTANT_U1;
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DU4 ICT_ADD_EQUAL_U4_CONSTANT_U1;
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DU4 ICT_ESI_ADD_EQUAL_U4_CONSTANT_U1;
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DU4 ICT_EDI_ADD_EQUAL_U4_CONSTANT_U1;
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DU4 ICT_TABLE_END;
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ICT_NULL:
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ICT_NOP:
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ICT_END_EXP:
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ICT_ZERO:
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|
ICT_U8:
|
|
ICT_U4:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,0x12345678
|
|
CDQ
|
|
ICT_U2:
|
|
ICT_U1:
|
|
ICT_DOUBLE:
|
|
ICT_STRING_CONSTANT:
|
|
ICT_EBP:
|
|
ICT_FS:
|
|
ICT_ESI:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,ESI
|
|
CDQ
|
|
ICT_EDI:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,EDI
|
|
CDQ
|
|
ICT_TO_DOUBLE:
|
|
ICT_TO_INT:
|
|
ICT_COM:
|
|
ICT_NOT:
|
|
ICT_UNARY_MINUS:
|
|
ICT_ADDRESS:
|
|
ICT_U8_DISP32:
|
|
ICT_U4_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,U4 0x12345678[EBP]
|
|
CDQ
|
|
ICT_U2_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOVSX EAX,U2 0x12345678[EBP]
|
|
CDQ
|
|
ICT_U1_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOVSX EAX,U1 0x12345678[EBP]
|
|
CDQ
|
|
ICT_U8_DISP8:
|
|
ICT_U4_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,U4 0x12[EBP]
|
|
CDQ
|
|
ICT_U2_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOVSX EAX,U2 0x12[EBP]
|
|
CDQ
|
|
ICT_U1_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOVSX EAX,U1 0x12[EBP]
|
|
CDQ
|
|
ICT_FS_U8_DISP32:
|
|
ICT_FS_U4_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,U4 FS:[0x12345678]
|
|
CDQ
|
|
ICT_FS_U2_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOVSX EAX,U2 FS:[0x12345678]
|
|
CDQ
|
|
ICT_FS_U1_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOVSX EAX,U1 FS:[0x12345678]
|
|
CDQ
|
|
ICT_ESI_U8_DISP32:
|
|
ICT_ESI_U4_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,U4 0x12345678[ESI]
|
|
CDQ
|
|
ICT_ESI_U2_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOVSX EAX,U2 0x12345678[ESI]
|
|
CDQ
|
|
ICT_ESI_U1_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOVSX EAX,U1 0x12345678[ESI]
|
|
CDQ
|
|
ICT_ESI_U8_DISP8:
|
|
ICT_ESI_U4_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,U4 0x12[ESI]
|
|
CDQ
|
|
ICT_ESI_U2_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOVSX EAX,U2 0x12[ESI]
|
|
CDQ
|
|
ICT_ESI_U1_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOVSX EAX,U1 0x12[ESI]
|
|
CDQ
|
|
ICT_EDI_U8_DISP32:
|
|
ICT_EDI_U4_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,U4 0x12345678[EDI]
|
|
CDQ
|
|
ICT_EDI_U2_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOVSX EAX,U2 0x12345678[EDI]
|
|
CDQ
|
|
ICT_EDI_U1_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOVSX EAX,U1 0x12345678[EDI]
|
|
CDQ
|
|
ICT_EDI_U8_DISP8:
|
|
ICT_EDI_U4_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,U4 0x12[EDI]
|
|
CDQ
|
|
ICT_EDI_U2_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOVSX EAX,U2 0x12[EDI]
|
|
CDQ
|
|
ICT_EDI_U1_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOVSX EAX,U1 0x12[EDI]
|
|
CDQ
|
|
ICT_DEREF_U8:
|
|
ICT_DEREF_U4:
|
|
MOV EAX,U4 [EAX]
|
|
CDQ
|
|
ICT_DEREF_U2:
|
|
MOVSX EAX,U2 [EAX]
|
|
CDQ
|
|
ICT_DEREF_U1:
|
|
MOVSX EAX,U1 [EAX]
|
|
CDQ
|
|
ICT_ESI_DEREF_U8:
|
|
ICT_ESI_DEREF_U4:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,U4 [ESI]
|
|
CDQ
|
|
ICT_ESI_DEREF_U2:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOVSX EAX,U2 [ESI]
|
|
CDQ
|
|
ICT_ESI_DEREF_U1:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOVSX EAX,U1 [ESI]
|
|
CDQ
|
|
ICT_EDI_DEREF_U8:
|
|
ICT_EDI_DEREF_U4:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,U4 [EDI]
|
|
CDQ
|
|
ICT_EDI_DEREF_U2:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOVSX EAX,U2 [EDI]
|
|
CDQ
|
|
ICT_EDI_DEREF_U1:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOVSX EAX,U1 [EDI]
|
|
CDQ
|
|
ICT_U8_PP:
|
|
ICT_U4_PP:
|
|
MOV EBX,EAX
|
|
MOV EAX,U4 [EBX]
|
|
INC U4 [EBX]
|
|
CDQ
|
|
ICT_U2_PP:
|
|
MOV EBX,EAX
|
|
MOVSX EAX,U2 [EBX]
|
|
INC U2 [EBX]
|
|
CDQ
|
|
ICT_U1_PP:
|
|
MOV EBX,EAX
|
|
MOVSX EAX,U1 [EBX]
|
|
INC U1 [EBX]
|
|
CDQ
|
|
ICT_U8_MM:
|
|
ICT_U4_MM:
|
|
MOV EBX,EAX
|
|
MOV EAX,U4 [EBX]
|
|
DEC U4 [EBX]
|
|
CDQ
|
|
ICT_U2_MM:
|
|
MOV EBX,EAX
|
|
MOVSX EAX,U2 [EBX]
|
|
DEC U2 [EBX]
|
|
CDQ
|
|
ICT_U1_MM:
|
|
MOV EBX,EAX
|
|
MOVSX EAX,U1 [EBX]
|
|
DEC U1 [EBX]
|
|
CDQ
|
|
ICT_PP_U8:
|
|
ICT_PP_U4:
|
|
INC U4 [EAX]
|
|
MOV EAX,U4 [EAX]
|
|
CDQ
|
|
ICT_PP_U2:
|
|
INC U2 [EAX]
|
|
MOVSX EAX,U2 [EAX]
|
|
CDQ
|
|
ICT_PP_U1:
|
|
INC U1 [EAX]
|
|
MOVSX EAX,U1 [EAX]
|
|
CDQ
|
|
ICT_MM_U8:
|
|
ICT_MM_U4:
|
|
DEC U4 [EAX]
|
|
MOV EAX,U4 [EAX]
|
|
CDQ
|
|
ICT_MM_U2:
|
|
DEC U2 [EAX]
|
|
MOVSX EAX,U2 [EAX]
|
|
CDQ
|
|
ICT_MM_U1:
|
|
DEC U1 [EAX]
|
|
MOVSX EAX,U1 [EAX]
|
|
CDQ
|
|
ICT_ESI_U4_PP:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,ESI
|
|
INC ESI
|
|
CDQ
|
|
ICT_ESI_U4_MM:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,ESI
|
|
DEC ESI
|
|
CDQ
|
|
ICT_ESI_PP_U4:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
INC ESI
|
|
MOV EAX,ESI
|
|
CDQ
|
|
ICT_ESI_MM_U4:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
DEC ESI
|
|
MOV EAX,ESI
|
|
CDQ
|
|
ICT_EDI_U4_PP:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,EDI
|
|
INC EDI
|
|
CDQ
|
|
ICT_EDI_U4_MM:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,EDI
|
|
DEC EDI
|
|
CDQ
|
|
ICT_EDI_PP_U4:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
INC EDI
|
|
MOV EAX,EDI
|
|
CDQ
|
|
ICT_EDI_MM_U4:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
DEC EDI
|
|
MOV EAX,EDI
|
|
CDQ
|
|
ICT_LEA_DISP32_EBP:
|
|
ICT_LEA_DISP8_EBP:
|
|
ICT_U8_DISP32_SCALED:
|
|
ICT_U4_DISP32_SCALED:
|
|
MOV EAX,U4 0x12345678[EAX*4]
|
|
CDQ
|
|
ICT_U2_DISP32_SCALED:
|
|
MOVSX EAX,U2 0x12345678[EAX*2]
|
|
CDQ
|
|
ICT_SHL:
|
|
ICT_SHR:
|
|
MOV ECX,EAX
|
|
POP EAX
|
|
POP EDX
|
|
SUB CL,32
|
|
JNC @@SR7
|
|
SHRD EAX,EDX
|
|
SAR EDX,CL
|
|
JMP ICT_SHL_CONSTANT1
|
|
@@SR7: MOV EAX,EDX
|
|
OR EDX,EDX
|
|
MOV EDX,0
|
|
JNS @@SR6
|
|
DEC EDX
|
|
@@SR6: SHRD EAX,EDX
|
|
ICT_SHL_CONSTANT1:
|
|
ICT_SHL_CONSTANT2:
|
|
ICT_SHR_CONSTANT1:
|
|
MOV CL,0x12
|
|
SHRD EAX,EDX
|
|
SAR EDX,CL
|
|
ICT_SHR_CONSTANT2:
|
|
MOV EAX,EDX
|
|
OR EDX,EDX
|
|
MOV EDX,0
|
|
JNS @@SC1
|
|
DEC EDX
|
|
@@SC1: MOV CL,0x12
|
|
SHRD EAX,EDX
|
|
ICT_POWER:
|
|
ICT_MULTIPLICATION:
|
|
POP EBX
|
|
ADD ESP,4
|
|
IMUL EBX
|
|
ICT_DIVISION:
|
|
MOV EBX,EAX
|
|
POP EAX
|
|
POP EDX
|
|
IDIV EBX
|
|
CDQ
|
|
ICT_REMAINDER:
|
|
MOV EBX,EAX
|
|
POP EAX
|
|
POP EDX
|
|
IDIV EBX
|
|
MOV EAX,EDX
|
|
CDQ
|
|
ICT_AND:
|
|
ICT_OR:
|
|
ICT_XOR:
|
|
ICT_ADDITION:
|
|
ICT_SUBTRACTION:
|
|
ICT_EQUAL_EQUAL:
|
|
ICT_NOT_EQUAL_TO:
|
|
ICT_LESS_THAN:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EBX,EAX
|
|
SBB ECX,EDX
|
|
MOV EAX,0
|
|
JGE @@LT1
|
|
INC EAX
|
|
@@LT1: XOR EDX,EDX
|
|
ICT_GREATER_THAN:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EAX,EBX
|
|
SBB EDX,ECX
|
|
MOV EAX,0
|
|
JGE @@GT1
|
|
INC EAX
|
|
@@GT1: XOR EDX,EDX
|
|
ICT_LESS_OR_EQUAL:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EAX,EBX
|
|
SBB EDX,ECX
|
|
MOV EAX,0
|
|
JL @@LE1
|
|
INC EAX
|
|
@@LE1: XOR EDX,EDX
|
|
ICT_GREATER_OR_EQUAL:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EBX,EAX
|
|
SBB ECX,EDX
|
|
MOV EAX,0
|
|
JL @@GE1
|
|
INC EAX
|
|
@@GE1: XOR EDX,EDX
|
|
ICT_AND_AND:
|
|
ICT_OR_OR:
|
|
ICT_XOR_XOR:
|
|
ICT_COLON:
|
|
ICT_QUESTION:
|
|
ICT_ASSIGN_U8:
|
|
ICT_ASSIGN_U4:
|
|
ICT_ASSIGN_U2:
|
|
ICT_ASSIGN_U1:
|
|
ICT_SHL_EQUAL_U8:
|
|
ICT_SHL_EQUAL_U4:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV CL,AL
|
|
SAL U4 [EBX],CL
|
|
MOV EAX,U4 [EBX]
|
|
CDQ
|
|
ICT_SHL_EQUAL_U2:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV CL,AL
|
|
SAL U2 [EBX],CL
|
|
MOVSX EAX,U2 [EBX]
|
|
CDQ
|
|
ICT_SHL_EQUAL_U1:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV CL,AL
|
|
SAL U1 [EBX],CL
|
|
MOVSX EAX,U1 [EBX]
|
|
CDQ
|
|
ICT_SHR_EQUAL_U8:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV ECX,EAX
|
|
MOV EAX,U4 [EBX]
|
|
MOV EDX,U4 4[EBX]
|
|
SUB ECX,32
|
|
JNC @@SR9
|
|
SHRD EAX,EDX
|
|
SAR EDX,CL
|
|
JMP @@SR10
|
|
@@SR9: MOV EAX,EDX
|
|
OR EDX,EDX
|
|
MOV EDX,0
|
|
JNS @@SR8
|
|
DEC EDX
|
|
@@SR8: SHRD EAX,EDX
|
|
@@SR10: MOV U4 [EBX],EAX
|
|
MOV U4 4[EBX],EDX
|
|
ICT_SHR_EQUAL_U4:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV CL,AL
|
|
SAR U4 [EBX],CL
|
|
MOV EAX,U4 [EBX]
|
|
CDQ
|
|
ICT_SHR_EQUAL_U2:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV CL,AL
|
|
SAR U2 [EBX],CL
|
|
MOVSX EAX,U2 [EBX]
|
|
CDQ
|
|
ICT_SHR_EQUAL_U1:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV CL,AL
|
|
SAR U1 [EBX],CL
|
|
MOVSX EAX,U1 [EBX]
|
|
CDQ
|
|
ICT_MUL_EQUAL_U8:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV EDX,U4 [EBX]
|
|
IMUL EDX
|
|
MOV U4 [EBX],EAX
|
|
MOV U4 4[EBX],EDX
|
|
ICT_MUL_EQUAL_U4:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV EDX,U4 [EBX]
|
|
IMUL EDX
|
|
MOV U4 [EBX],EAX
|
|
ICT_MUL_EQUAL_U2:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOVSX EDX,U2 [EBX]
|
|
IMUL EDX
|
|
MOV U2 [EBX],AX
|
|
ICT_MUL_EQUAL_U1:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOVSX EDX,U1 [EBX]
|
|
IMUL EDX
|
|
MOV U1 [EBX],AL
|
|
ICT_DIV_EQUAL_U8:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV ECX,EAX
|
|
MOV EAX,U4 [EBX]
|
|
MOV EDX,U4 4[EBX]
|
|
IDIV ECX
|
|
MOV U4 [EBX],EAX
|
|
CDQ
|
|
MOV U4 4[EBX],EDX
|
|
ICT_DIV_EQUAL_U4:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV ECX,EAX
|
|
MOV EAX,U4 [EBX]
|
|
CDQ
|
|
IDIV ECX
|
|
MOV U4 [EBX],EAX
|
|
CDQ
|
|
ICT_DIV_EQUAL_U2:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV ECX,EAX
|
|
MOVSX EAX,U2 [EBX]
|
|
CDQ
|
|
IDIV ECX
|
|
MOV U2 [EBX],AX
|
|
MOVSX EAX,AX
|
|
CDQ
|
|
ICT_DIV_EQUAL_U1:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV ECX,EAX
|
|
MOVSX EAX,U1 [EBX]
|
|
CDQ
|
|
IDIV ECX
|
|
MOV U1 [EBX],AL
|
|
MOVSX EAX,AL
|
|
CDQ
|
|
ICT_AND_EQUAL_U8:
|
|
ICT_AND_EQUAL_U4:
|
|
ICT_AND_EQUAL_U2:
|
|
ICT_AND_EQUAL_U1:
|
|
ICT_OR_EQUAL_U8:
|
|
ICT_OR_EQUAL_U4:
|
|
ICT_OR_EQUAL_U2:
|
|
ICT_OR_EQUAL_U1:
|
|
ICT_XOR_EQUAL_U8:
|
|
ICT_XOR_EQUAL_U4:
|
|
ICT_XOR_EQUAL_U2:
|
|
ICT_XOR_EQUAL_U1:
|
|
ICT_ADD_EQUAL_U8:
|
|
ICT_ADD_EQUAL_U4:
|
|
POP EBX
|
|
ADD ESP,4
|
|
ADD U4 [EBX],EAX
|
|
MOV EAX,U4 [EBX]
|
|
CDQ
|
|
ICT_ADD_EQUAL_U2:
|
|
POP EBX
|
|
ADD ESP,4
|
|
ADD U2 [EBX],AX
|
|
MOVSX EAX,U2 [EBX]
|
|
CDQ
|
|
ICT_ADD_EQUAL_U1:
|
|
POP EBX
|
|
ADD ESP,4
|
|
ADD U1 [EBX],AL
|
|
MOVSX EAX,U1 [EBX]
|
|
CDQ
|
|
ICT_SUB_EQUAL_U8:
|
|
ICT_SUB_EQUAL_U4:
|
|
POP EBX
|
|
ADD ESP,4
|
|
SUB U4 [EBX],EAX
|
|
MOV EAX,U4 [EBX]
|
|
CDQ
|
|
ICT_SUB_EQUAL_U2:
|
|
POP EBX
|
|
ADD ESP,4
|
|
SUB U2 [EBX],AX
|
|
MOVSX EAX,U2 [EBX]
|
|
CDQ
|
|
ICT_SUB_EQUAL_U1:
|
|
POP EBX
|
|
ADD ESP,4
|
|
SUB U1 [EBX],AL
|
|
MOVSX EAX,U1 [EBX]
|
|
CDQ
|
|
ICT_ESI_ASSIGN_U4:
|
|
ICT_ESI_SHL_EQUAL_U4:
|
|
MOV ECX,EAX
|
|
SHL ESI,CL
|
|
MOV EAX,ESI
|
|
CDQ
|
|
ICT_ESI_SHR_EQUAL_U4:
|
|
MOV ECX,EAX
|
|
SAR ESI,CL
|
|
MOV EAX,ESI
|
|
CDQ
|
|
ICT_ESI_MUL_EQUAL_U4:
|
|
MOV EDX,ESI
|
|
IMUL EDX
|
|
MOV ESI,EAX
|
|
CDQ
|
|
ICT_ESI_DIV_EQUAL_U4:
|
|
MOV ECX,EAX
|
|
MOV EAX,ESI
|
|
XOR EDX,EDX
|
|
IDIV ECX
|
|
MOV ESI,EAX
|
|
CDQ
|
|
ICT_ESI_AND_EQUAL_U4:
|
|
AND ESI,EAX
|
|
MOV EAX,ESI
|
|
CDQ
|
|
ICT_ESI_OR_EQUAL_U4:
|
|
OR ESI,EAX
|
|
MOV EAX,ESI
|
|
CDQ
|
|
ICT_ESI_XOR_EQUAL_U4:
|
|
XOR ESI,EAX
|
|
MOV EAX,ESI
|
|
CDQ
|
|
ICT_ESI_ADD_EQUAL_U4:
|
|
ADD ESI,EAX
|
|
MOV EAX,ESI
|
|
CDQ
|
|
ICT_ESI_SUB_EQUAL_U4:
|
|
SUB ESI,EAX
|
|
MOV EAX,ESI
|
|
CDQ
|
|
ICT_EDI_ASSIGN_U4:
|
|
ICT_EDI_SHL_EQUAL_U4:
|
|
MOV ECX,EAX
|
|
SHL EDI,CL
|
|
MOV EAX,EDI
|
|
CDQ
|
|
ICT_EDI_SHR_EQUAL_U4:
|
|
MOV ECX,EAX
|
|
SAR EDI,CL
|
|
MOV EAX,EDI
|
|
CDQ
|
|
ICT_EDI_MUL_EQUAL_U4:
|
|
MOV EDX,EDI
|
|
IMUL EDX
|
|
MOV EDI,EAX
|
|
CDQ
|
|
ICT_EDI_DIV_EQUAL_U4:
|
|
MOV ECX,EAX
|
|
MOV EAX,EDI
|
|
XOR EDX,EDX
|
|
IDIV ECX
|
|
MOV EDI,EAX
|
|
CDQ
|
|
ICT_EDI_AND_EQUAL_U4:
|
|
AND EDI,EAX
|
|
MOV EAX,EDI
|
|
CDQ
|
|
ICT_EDI_OR_EQUAL_U4:
|
|
OR EDI,EAX
|
|
MOV EAX,EDI
|
|
CDQ
|
|
ICT_EDI_XOR_EQUAL_U4:
|
|
XOR EDI,EAX
|
|
MOV EAX,EDI
|
|
CDQ
|
|
ICT_EDI_ADD_EQUAL_U4:
|
|
ADD EDI,EAX
|
|
MOV EAX,EDI
|
|
CDQ
|
|
ICT_EDI_SUB_EQUAL_U4:
|
|
SUB EDI,EAX
|
|
MOV EAX,EDI
|
|
CDQ
|
|
ICT_ADD64:
|
|
ICT_ADD32:
|
|
ICT_ADD8:
|
|
ICT_INC:
|
|
ICT_SUB64:
|
|
ICT_SUB32:
|
|
ICT_SUB8:
|
|
ICT_DEC:
|
|
ICT_ENTER:
|
|
ICT_LEAVE:
|
|
ICT_ENTER1:
|
|
ICT_LEAVE1:
|
|
ICT_ENTER2:
|
|
ICT_LEAVE2:
|
|
ICT_ADD_ESP32:
|
|
ICT_ADD_ESP8:
|
|
ICT_RET:
|
|
ICT_CALL:
|
|
ICT_CALL_INDIRECT:
|
|
ICT_CALL_INDIRECT2:
|
|
ICT_IRQ:
|
|
ICT_CLI:
|
|
ICT_STI:
|
|
ICT_GET_FLAGS:
|
|
ICT_SET_FLAGS:
|
|
ICT_GET_BASE_PTR:
|
|
ICT_SET_BASE_PTR:
|
|
ICT_GET_STACK_PTR:
|
|
ICT_SET_STACK_PTR:
|
|
ICT_GET_LABEL:
|
|
ICT_ABSOLUTE_ADDRESS:
|
|
ICT_LABEL:
|
|
ICT_TYPE:
|
|
ICT_BT:
|
|
ICT_BTS:
|
|
ICT_BTR:
|
|
ICT_BTC:
|
|
ICT_BSF:
|
|
ICT_BSR:
|
|
ICT_INSQUE:
|
|
ICT_INSQUE_REV:
|
|
ICT_REMQUE:
|
|
ICT_STRLEN:
|
|
ICT_MEMCPY:
|
|
ICT_MEMSET:
|
|
ICT_INPD:
|
|
ICT_INPW:
|
|
ICT_INP:
|
|
ICT_OUTPD:
|
|
ICT_OUTPW:
|
|
ICT_OUTP:
|
|
ICT_JMP:
|
|
ICT_SHORT_JMP:
|
|
ICT_SWITCH:
|
|
ICT_SKIPZ:
|
|
ICT_SKIPZ2:
|
|
ICT_SKIPNZ:
|
|
ICT_SKIPNZ2:
|
|
ICT_EQUAL_EQUAL_SKIPZ:
|
|
ICT_EQUAL_EQUAL_SKIPZ2:
|
|
ICT_NOT_EQUAL_TO_SKIPZ:
|
|
ICT_NOT_EQUAL_TO_SKIPZ2:
|
|
ICT_LESS_THAN_SKIPZ:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EBX,EAX
|
|
SBB ECX,EDX
|
|
JGE ICT_LESS_THAN_SKIPZ
|
|
ICT_LESS_THAN_SKIPZ2:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EBX,EAX
|
|
SBB ECX,EDX
|
|
JGE U4 FAR_AWAY
|
|
ICT_GREATER_THAN_SKIPZ:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EAX,EBX
|
|
SBB EDX,ECX
|
|
JGE ICT_GREATER_THAN_SKIPZ
|
|
ICT_GREATER_THAN_SKIPZ2:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EAX,EBX
|
|
SBB EDX,ECX
|
|
JGE U4 FAR_AWAY
|
|
ICT_LESS_OR_EQUAL_SKIPZ:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EAX,EBX
|
|
SBB EDX,ECX
|
|
JL ICT_LESS_OR_EQUAL_SKIPZ
|
|
ICT_LESS_OR_EQUAL_SKIPZ2:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EAX,EBX
|
|
SBB EDX,ECX
|
|
JL U4 FAR_AWAY
|
|
ICT_GREATER_OR_EQUAL_SKIPZ:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EBX,EAX
|
|
SBB ECX,EDX
|
|
JL ICT_GREATER_OR_EQUAL_SKIPZ
|
|
ICT_GREATER_OR_EQUAL_SKIPZ2:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EBX,EAX
|
|
SBB ECX,EDX
|
|
JL U4 FAR_AWAY
|
|
ICT_AND_AND_SKIPZ:
|
|
ICT_AND_AND_SKIPZ2:
|
|
ICT_AND_AND_SKIPNZ:
|
|
ICT_AND_AND_SKIPNZ2:
|
|
ICT_OR_OR_SKIPZ:
|
|
ICT_OR_OR_SKIPZ2:
|
|
ICT_OR_OR_SKIPNZ:
|
|
ICT_OR_OR_SKIPNZ2:
|
|
ICT_LEA_DISP32_ESI:
|
|
ICT_LEA_DISP8_ESI:
|
|
ICT_LEA_DISP32_EDI:
|
|
ICT_LEA_DISP8_EDI:
|
|
ICT_PUSH_U8:
|
|
ICT_PUSH_U4:
|
|
ICT_PUSH_U2:
|
|
ICT_PUSH_U1:
|
|
ICT_PUSH_NEG_U4:
|
|
ICT_PUSH_NEG_U2:
|
|
ICT_PUSH_NEG_U1:
|
|
ICT_PUSH_DOUBLE:
|
|
ICT_PUSH_U8_DISP32:
|
|
ICT_PUSH_U8_DISP8:
|
|
ICT_PUSH_ESI_U8_DISP32:
|
|
ICT_PUSH_ESI_U8_DISP8:
|
|
ICT_PUSH_EDI_U8_DISP32:
|
|
ICT_PUSH_EDI_U8_DISP8:
|
|
ICT_PUSH_DEREF_U8:
|
|
ICT_PUSH_U8_DISP32_SCALED:
|
|
ICT_BT_CONSTANT:
|
|
ICT_BTS_CONSTANT:
|
|
ICT_BTR_CONSTANT:
|
|
ICT_BTC_CONSTANT:
|
|
ICT_ESI_NEXT_EQUAL_U4:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV ESI,U4 [ESI]
|
|
MOV EAX,ESI
|
|
CDQ
|
|
ICT_EDI_NEXT_EQUAL_U4:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EDI,U4 [EDI]
|
|
MOV EAX,EDI
|
|
CDQ
|
|
ICT_ADD_EQUAL_U8_CONSTANT_U1:
|
|
ICT_SUB_EQUAL_U8_CONSTANT_U1:
|
|
ICT_ADD_EQUAL_U4_CONSTANT_U1:
|
|
ADD U4 [EAX],0x12
|
|
MOV EAX,U4 [EAX]
|
|
CDQ
|
|
ICT_ESI_ADD_EQUAL_U4_CONSTANT_U1:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
ADD ESI,0x12
|
|
MOV EAX,ESI
|
|
CDQ
|
|
ICT_EDI_ADD_EQUAL_U4_CONSTANT_U1:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
ADD EDI,0x12
|
|
MOV EAX,EDI
|
|
CDQ
|
|
ICT_TABLE_END:
|
|
|
|
ALIGN 8,0x90
|
|
UNSIGNED_CODE_TABLE::
|
|
DU4 UCT_NULL;
|
|
DU4 UCT_NOP;
|
|
DU4 UCT_END_EXP;
|
|
DU4 UCT_ZERO;
|
|
DU4 UCT_U8;
|
|
DU4 UCT_U4;
|
|
DU4 UCT_U2;
|
|
DU4 UCT_U1;
|
|
DU4 UCT_DOUBLE;
|
|
DU4 UCT_STRING_CONSTANT;
|
|
DU4 UCT_EBP;
|
|
DU4 UCT_FS;
|
|
DU4 UCT_ESI;
|
|
DU4 UCT_EDI;
|
|
DU4 UCT_TO_DOUBLE;
|
|
DU4 UCT_TO_INT;
|
|
DU4 UCT_COM;
|
|
DU4 UCT_NOT;
|
|
DU4 UCT_UNARY_MINUS;
|
|
DU4 UCT_ADDRESS;
|
|
DU4 UCT_U8_DISP32;
|
|
DU4 UCT_U4_DISP32;
|
|
DU4 UCT_U2_DISP32;
|
|
DU4 UCT_U1_DISP32;
|
|
DU4 UCT_U8_DISP8;
|
|
DU4 UCT_U4_DISP8;
|
|
DU4 UCT_U2_DISP8;
|
|
DU4 UCT_U1_DISP8;
|
|
DU4 UCT_FS_U8_DISP32;
|
|
DU4 UCT_FS_U4_DISP32;
|
|
DU4 UCT_FS_U2_DISP32;
|
|
DU4 UCT_FS_U1_DISP32;
|
|
DU4 UCT_ESI_U8_DISP32;
|
|
DU4 UCT_ESI_U4_DISP32;
|
|
DU4 UCT_ESI_U2_DISP32;
|
|
DU4 UCT_ESI_U1_DISP32;
|
|
DU4 UCT_ESI_U8_DISP8;
|
|
DU4 UCT_ESI_U4_DISP8;
|
|
DU4 UCT_ESI_U2_DISP8;
|
|
DU4 UCT_ESI_U1_DISP8;
|
|
DU4 UCT_EDI_U8_DISP32;
|
|
DU4 UCT_EDI_U4_DISP32;
|
|
DU4 UCT_EDI_U2_DISP32;
|
|
DU4 UCT_EDI_U1_DISP32;
|
|
DU4 UCT_EDI_U8_DISP8;
|
|
DU4 UCT_EDI_U4_DISP8;
|
|
DU4 UCT_EDI_U2_DISP8;
|
|
DU4 UCT_EDI_U1_DISP8;
|
|
DU4 UCT_DEREF_U8;
|
|
DU4 UCT_DEREF_U4;
|
|
DU4 UCT_DEREF_U2;
|
|
DU4 UCT_DEREF_U1;
|
|
DU4 UCT_ESI_DEREF_U8;
|
|
DU4 UCT_ESI_DEREF_U4;
|
|
DU4 UCT_ESI_DEREF_U2;
|
|
DU4 UCT_ESI_DEREF_U1;
|
|
DU4 UCT_EDI_DEREF_U8;
|
|
DU4 UCT_EDI_DEREF_U4;
|
|
DU4 UCT_EDI_DEREF_U2;
|
|
DU4 UCT_EDI_DEREF_U1;
|
|
DU4 UCT_U8_PP;
|
|
DU4 UCT_U4_PP;
|
|
DU4 UCT_U2_PP;
|
|
DU4 UCT_U1_PP;
|
|
DU4 UCT_U8_MM;
|
|
DU4 UCT_U4_MM;
|
|
DU4 UCT_U2_MM;
|
|
DU4 UCT_U1_MM;
|
|
DU4 UCT_PP_U8;
|
|
DU4 UCT_PP_U4;
|
|
DU4 UCT_PP_U2;
|
|
DU4 UCT_PP_U1;
|
|
DU4 UCT_MM_U8;
|
|
DU4 UCT_MM_U4;
|
|
DU4 UCT_MM_U2;
|
|
DU4 UCT_MM_U1;
|
|
DU4 UCT_ESI_U4_PP;
|
|
DU4 UCT_ESI_U4_MM;
|
|
DU4 UCT_ESI_PP_U4;
|
|
DU4 UCT_ESI_MM_U4;
|
|
DU4 UCT_EDI_U4_PP;
|
|
DU4 UCT_EDI_U4_MM;
|
|
DU4 UCT_EDI_PP_U4;
|
|
DU4 UCT_EDI_MM_U4;
|
|
DU4 UCT_LEA_DISP32_EBP;
|
|
DU4 UCT_LEA_DISP8_EBP;
|
|
DU4 UCT_U8_DISP32_SCALED;
|
|
DU4 UCT_U4_DISP32_SCALED;
|
|
DU4 UCT_U2_DISP32_SCALED;
|
|
DU4 UCT_SHL;
|
|
DU4 UCT_SHR;
|
|
DU4 UCT_SHL_CONSTANT1;
|
|
DU4 UCT_SHL_CONSTANT2;
|
|
DU4 UCT_SHR_CONSTANT1;
|
|
DU4 UCT_SHR_CONSTANT2;
|
|
DU4 UCT_POWER;
|
|
DU4 UCT_MULTIPLICATION;
|
|
DU4 UCT_DIVISION;
|
|
DU4 UCT_REMAINDER;
|
|
DU4 UCT_AND;
|
|
DU4 UCT_OR;
|
|
DU4 UCT_XOR;
|
|
DU4 UCT_ADDITION;
|
|
DU4 UCT_SUBTRACTION;
|
|
DU4 UCT_EQUAL_EQUAL;
|
|
DU4 UCT_NOT_EQUAL_TO;
|
|
DU4 UCT_LESS_THAN;
|
|
DU4 UCT_GREATER_THAN;
|
|
DU4 UCT_LESS_OR_EQUAL;
|
|
DU4 UCT_GREATER_OR_EQUAL;
|
|
DU4 UCT_AND_AND;
|
|
DU4 UCT_OR_OR;
|
|
DU4 UCT_XOR_XOR;
|
|
DU4 UCT_COLON;
|
|
DU4 UCT_QUESTION;
|
|
DU4 UCT_ASSIGN_U8;
|
|
DU4 UCT_ASSIGN_U4;
|
|
DU4 UCT_ASSIGN_U2;
|
|
DU4 UCT_ASSIGN_U1;
|
|
DU4 UCT_SHL_EQUAL_U8;
|
|
DU4 UCT_SHL_EQUAL_U4;
|
|
DU4 UCT_SHL_EQUAL_U2;
|
|
DU4 UCT_SHL_EQUAL_U1;
|
|
DU4 UCT_SHR_EQUAL_U8;
|
|
DU4 UCT_SHR_EQUAL_U4;
|
|
DU4 UCT_SHR_EQUAL_U2;
|
|
DU4 UCT_SHR_EQUAL_U1;
|
|
DU4 UCT_MUL_EQUAL_U8;
|
|
DU4 UCT_MUL_EQUAL_U4;
|
|
DU4 UCT_MUL_EQUAL_U2;
|
|
DU4 UCT_MUL_EQUAL_U1;
|
|
DU4 UCT_DIV_EQUAL_U8;
|
|
DU4 UCT_DIV_EQUAL_U4;
|
|
DU4 UCT_DIV_EQUAL_U2;
|
|
DU4 UCT_DIV_EQUAL_U1;
|
|
DU4 UCT_AND_EQUAL_U8;
|
|
DU4 UCT_AND_EQUAL_U4;
|
|
DU4 UCT_AND_EQUAL_U2;
|
|
DU4 UCT_AND_EQUAL_U1;
|
|
DU4 UCT_OR_EQUAL_U8;
|
|
DU4 UCT_OR_EQUAL_U4;
|
|
DU4 UCT_OR_EQUAL_U2;
|
|
DU4 UCT_OR_EQUAL_U1;
|
|
DU4 UCT_XOR_EQUAL_U8;
|
|
DU4 UCT_XOR_EQUAL_U4;
|
|
DU4 UCT_XOR_EQUAL_U2;
|
|
DU4 UCT_XOR_EQUAL_U1;
|
|
DU4 UCT_ADD_EQUAL_U8;
|
|
DU4 UCT_ADD_EQUAL_U4;
|
|
DU4 UCT_ADD_EQUAL_U2;
|
|
DU4 UCT_ADD_EQUAL_U1;
|
|
DU4 UCT_SUB_EQUAL_U8;
|
|
DU4 UCT_SUB_EQUAL_U4;
|
|
DU4 UCT_SUB_EQUAL_U2;
|
|
DU4 UCT_SUB_EQUAL_U1;
|
|
DU4 UCT_ESI_ASSIGN_U4;
|
|
DU4 UCT_ESI_SHL_EQUAL_U4;
|
|
DU4 UCT_ESI_SHR_EQUAL_U4;
|
|
DU4 UCT_ESI_MUL_EQUAL_U4;
|
|
DU4 UCT_ESI_DIV_EQUAL_U4;
|
|
DU4 UCT_ESI_AND_EQUAL_U4;
|
|
DU4 UCT_ESI_OR_EQUAL_U4;
|
|
DU4 UCT_ESI_XOR_EQUAL_U4;
|
|
DU4 UCT_ESI_ADD_EQUAL_U4;
|
|
DU4 UCT_ESI_SUB_EQUAL_U4;
|
|
DU4 UCT_EDI_ASSIGN_U4;
|
|
DU4 UCT_EDI_SHL_EQUAL_U4;
|
|
DU4 UCT_EDI_SHR_EQUAL_U4;
|
|
DU4 UCT_EDI_MUL_EQUAL_U4;
|
|
DU4 UCT_EDI_DIV_EQUAL_U4;
|
|
DU4 UCT_EDI_AND_EQUAL_U4;
|
|
DU4 UCT_EDI_OR_EQUAL_U4;
|
|
DU4 UCT_EDI_XOR_EQUAL_U4;
|
|
DU4 UCT_EDI_ADD_EQUAL_U4;
|
|
DU4 UCT_EDI_SUB_EQUAL_U4;
|
|
DU4 UCT_ADD64;
|
|
DU4 UCT_ADD32;
|
|
DU4 UCT_ADD8;
|
|
DU4 UCT_INC;
|
|
DU4 UCT_SUB64;
|
|
DU4 UCT_SUB32;
|
|
DU4 UCT_SUB8;
|
|
DU4 UCT_DEC;
|
|
DU4 UCT_ENTER;
|
|
DU4 UCT_LEAVE;
|
|
DU4 UCT_ENTER1;
|
|
DU4 UCT_LEAVE1;
|
|
DU4 UCT_ENTER2;
|
|
DU4 UCT_LEAVE2;
|
|
DU4 UCT_ADD_ESP32;
|
|
DU4 UCT_ADD_ESP8;
|
|
DU4 UCT_RET;
|
|
DU4 UCT_CALL;
|
|
DU4 UCT_CALL_INDIRECT;
|
|
DU4 UCT_CALL_INDIRECT2;
|
|
DU4 UCT_IRQ;
|
|
DU4 UCT_CLI;
|
|
DU4 UCT_STI;
|
|
DU4 UCT_GET_FLAGS;
|
|
DU4 UCT_SET_FLAGS;
|
|
DU4 UCT_GET_BASE_PTR;
|
|
DU4 UCT_SET_BASE_PTR;
|
|
DU4 UCT_GET_STACK_PTR;
|
|
DU4 UCT_SET_STACK_PTR;
|
|
DU4 UCT_GET_LABEL;
|
|
DU4 UCT_ABSOLUTE_ADDRESS;
|
|
DU4 UCT_LABEL;
|
|
DU4 UCT_TYPE;
|
|
DU4 UCT_BT;
|
|
DU4 UCT_BTS;
|
|
DU4 UCT_BTR;
|
|
DU4 UCT_BTC;
|
|
DU4 UCT_BSF;
|
|
DU4 UCT_BSR;
|
|
DU4 UCT_INSQUE;
|
|
DU4 UCT_INSQUE_REV;
|
|
DU4 UCT_REMQUE;
|
|
DU4 UCT_STRLEN;
|
|
DU4 UCT_MEMCPY;
|
|
DU4 UCT_MEMSET;
|
|
DU4 UCT_INPD;
|
|
DU4 UCT_INPW;
|
|
DU4 UCT_INP;
|
|
DU4 UCT_OUTPD;
|
|
DU4 UCT_OUTPW;
|
|
DU4 UCT_OUTP;
|
|
DU4 UCT_JMP;
|
|
DU4 UCT_SHORT_JMP;
|
|
DU4 UCT_SWITCH;
|
|
DU4 UCT_SKIPZ;
|
|
DU4 UCT_SKIPZ2;
|
|
DU4 UCT_SKIPNZ;
|
|
DU4 UCT_SKIPNZ2;
|
|
DU4 UCT_EQUAL_EQUAL_SKIPZ;
|
|
DU4 UCT_EQUAL_EQUAL_SKIPZ2;
|
|
DU4 UCT_NOT_EQUAL_TO_SKIPZ;
|
|
DU4 UCT_NOT_EQUAL_TO_SKIPZ2;
|
|
DU4 UCT_LESS_THAN_SKIPZ;
|
|
DU4 UCT_LESS_THAN_SKIPZ2;
|
|
DU4 UCT_GREATER_THAN_SKIPZ;
|
|
DU4 UCT_GREATER_THAN_SKIPZ2;
|
|
DU4 UCT_LESS_OR_EQUAL_SKIPZ;
|
|
DU4 UCT_LESS_OR_EQUAL_SKIPZ2;
|
|
DU4 UCT_GREATER_OR_EQUAL_SKIPZ;
|
|
DU4 UCT_GREATER_OR_EQUAL_SKIPZ2;
|
|
DU4 UCT_AND_AND_SKIPZ;
|
|
DU4 UCT_AND_AND_SKIPZ2;
|
|
DU4 UCT_AND_AND_SKIPNZ;
|
|
DU4 UCT_AND_AND_SKIPNZ2;
|
|
DU4 UCT_OR_OR_SKIPZ;
|
|
DU4 UCT_OR_OR_SKIPZ2;
|
|
DU4 UCT_OR_OR_SKIPNZ;
|
|
DU4 UCT_OR_OR_SKIPNZ2;
|
|
DU4 UCT_LEA_DISP32_ESI;
|
|
DU4 UCT_LEA_DISP8_ESI;
|
|
DU4 UCT_LEA_DISP32_EDI;
|
|
DU4 UCT_LEA_DISP8_EDI;
|
|
DU4 UCT_PUSH_U8;
|
|
DU4 UCT_PUSH_U4;
|
|
DU4 UCT_PUSH_U2;
|
|
DU4 UCT_PUSH_U1;
|
|
DU4 UCT_PUSH_NEG_U4;
|
|
DU4 UCT_PUSH_NEG_U2;
|
|
DU4 UCT_PUSH_NEG_U1;
|
|
DU4 UCT_PUSH_DOUBLE;
|
|
DU4 UCT_PUSH_U8_DISP32;
|
|
DU4 UCT_PUSH_U8_DISP8;
|
|
DU4 UCT_PUSH_ESI_U8_DISP32;
|
|
DU4 UCT_PUSH_ESI_U8_DISP8;
|
|
DU4 UCT_PUSH_EDI_U8_DISP32;
|
|
DU4 UCT_PUSH_EDI_U8_DISP8;
|
|
DU4 UCT_PUSH_DEREF_U8;
|
|
DU4 UCT_PUSH_U8_DISP32_SCALED;
|
|
DU4 UCT_BT_CONSTANT;
|
|
DU4 UCT_BTS_CONSTANT;
|
|
DU4 UCT_BTR_CONSTANT;
|
|
DU4 UCT_BTC_CONSTANT;
|
|
DU4 UCT_ESI_NEXT_EQUAL_U4;
|
|
DU4 UCT_EDI_NEXT_EQUAL_U4;
|
|
DU4 UCT_ADD_EQUAL_U8_CONSTANT_U1;
|
|
DU4 UCT_SUB_EQUAL_U8_CONSTANT_U1;
|
|
DU4 UCT_ADD_EQUAL_U4_CONSTANT_U1;
|
|
DU4 UCT_ESI_ADD_EQUAL_U4_CONSTANT_U1;
|
|
DU4 UCT_EDI_ADD_EQUAL_U4_CONSTANT_U1;
|
|
DU4 UCT_TABLE_END;
|
|
UCT_NULL:
|
|
UCT_NOP:
|
|
UCT_END_EXP:
|
|
UCT_ZERO:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EAX,EAX
|
|
XOR EDX,EDX
|
|
UCT_U8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EDX,0x12345678
|
|
MOV EAX,0x9ABCDEF0
|
|
UCT_U4:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOV EAX,0x12345678
|
|
UCT_U2: //not used
|
|
UCT_U1:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
LEA EAX,0x12[EDX]
|
|
UCT_DOUBLE:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EDX,0x12345678
|
|
MOV EAX,0x9ABCDEF0
|
|
UCT_STRING_CONSTANT:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOV EAX,0x12345678
|
|
UCT_EBP:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOV EAX,EBP
|
|
UCT_FS:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOV EAX,U4 FS:[TSS_ABSOLUTE_ADDRESS]
|
|
UCT_ESI:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,ESI
|
|
XOR EDX,EDX
|
|
UCT_EDI:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,EDI
|
|
XOR EDX,EDX
|
|
UCT_TO_DOUBLE:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FILD U4 4[EBP]
|
|
FSTP U4 4[EBP]
|
|
POP EBP
|
|
POP EAX
|
|
POP EDX
|
|
UCT_TO_INT:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 4[EBP]
|
|
FISTP U4 4[EBP]
|
|
POP EBP
|
|
POP EAX
|
|
POP EDX
|
|
UCT_COM:
|
|
NOT EAX
|
|
NOT EDX
|
|
UCT_NOT:
|
|
OR EAX,EDX
|
|
MOV EAX,1
|
|
JZ @@N1
|
|
XOR EAX,EAX
|
|
@@N1: XOR EDX,EDX
|
|
UCT_UNARY_MINUS:
|
|
NEG EAX
|
|
JC @@UM2
|
|
DEC EDX
|
|
@@UM2: NOT EDX
|
|
UCT_ADDRESS:
|
|
UCT_U8_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
LEA EAX,U4 0x12345678[EBP]
|
|
MOV EDX,U4 4[EAX]
|
|
MOV EAX,U4 [EAX]
|
|
UCT_U4_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOV EAX,U4 0x12345678[EBP]
|
|
UCT_U2_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOVZX EAX,U2 0x12345678[EBP]
|
|
UCT_U1_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOVZX EAX,U1 0x12345678[EBP]
|
|
UCT_U8_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
LEA EAX,U4 0x12[EBP]
|
|
MOV EDX,U4 4[EAX]
|
|
MOV EAX,U4 [EAX]
|
|
UCT_U4_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOV EAX,U4 0x12[EBP]
|
|
UCT_U2_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOVZX EAX,U2 0x12[EBP]
|
|
UCT_U1_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOVZX EAX,U1 0x12[EBP]
|
|
UCT_FS_U8_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EDX,U4 FS:[0x12345678+4]
|
|
MOV EAX,U4 FS:[0x12345678]
|
|
UCT_FS_U4_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOV EAX,U4 FS:[0x12345678]
|
|
UCT_FS_U2_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOVZX EAX,U2 FS:[0x12345678]
|
|
UCT_FS_U1_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOVZX EAX,U1 FS:[0x12345678]
|
|
UCT_ESI_U8_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
LEA EAX,U4 0x12345678[ESI]
|
|
MOV EDX,U4 4[EAX]
|
|
MOV EAX,U4 [EAX]
|
|
UCT_ESI_U4_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOV EAX,U4 0x12345678[ESI]
|
|
UCT_ESI_U2_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOVZX EAX,U2 0x12345678[ESI]
|
|
UCT_ESI_U1_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOVZX EAX,U1 0x12345678[ESI]
|
|
UCT_ESI_U8_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
LEA EAX,U4 0x12[ESI]
|
|
MOV EDX,U4 4[EAX]
|
|
MOV EAX,U4 [EAX]
|
|
UCT_ESI_U4_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOV EAX,U4 0x12[ESI]
|
|
UCT_ESI_U2_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOVZX EAX,U2 0x12[ESI]
|
|
UCT_ESI_U1_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOVZX EAX,U1 0x12[ESI]
|
|
UCT_EDI_U8_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
LEA EAX,U4 0x12345678[EDI]
|
|
MOV EDX,U4 4[EAX]
|
|
MOV EAX,U4 [EAX]
|
|
UCT_EDI_U4_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOV EAX,U4 0x12345678[EDI]
|
|
UCT_EDI_U2_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOVZX EAX,U2 0x12345678[EDI]
|
|
UCT_EDI_U1_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOVZX EAX,U1 0x12345678[EDI]
|
|
UCT_EDI_U8_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
LEA EAX,U4 0x12[EDI]
|
|
MOV EDX,U4 4[EAX]
|
|
MOV EAX,U4 [EAX]
|
|
UCT_EDI_U4_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOV EAX,U4 0x12[EDI]
|
|
UCT_EDI_U2_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOVZX EAX,U2 0x12[EDI]
|
|
UCT_EDI_U1_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOVZX EAX,U1 0x12[EDI]
|
|
UCT_DEREF_U8:
|
|
MOV EDX,U4 4[EAX]
|
|
MOV EAX,U4 [EAX]
|
|
UCT_DEREF_U4:
|
|
XOR EDX,EDX
|
|
MOV EAX,U4 [EAX]
|
|
UCT_DEREF_U2:
|
|
XOR EDX,EDX
|
|
MOVZX EAX,U2 [EAX]
|
|
UCT_DEREF_U1:
|
|
XOR EDX,EDX
|
|
MOVZX EAX,U1 [EAX]
|
|
UCT_ESI_DEREF_U8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EDX,U4 4[ESI]
|
|
MOV EAX,U4 [ESI]
|
|
UCT_ESI_DEREF_U4:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOV EAX,U4 [ESI]
|
|
UCT_ESI_DEREF_U2:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOVZX EAX,U2 [ESI]
|
|
UCT_ESI_DEREF_U1:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOVZX EAX,U1 [ESI]
|
|
UCT_EDI_DEREF_U8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EDX,U4 4[EDI]
|
|
MOV EAX,U4 [EDI]
|
|
UCT_EDI_DEREF_U4:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOV EAX,U4 [EDI]
|
|
UCT_EDI_DEREF_U2:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOVZX EAX,U2 [EDI]
|
|
UCT_EDI_DEREF_U1:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOVZX EAX,U1 [EDI]
|
|
UCT_U8_PP:
|
|
MOV EBX,EAX
|
|
MOV EAX,U4 [EBX]
|
|
MOV EDX,U4 4[EBX]
|
|
INC U4 [EBX]
|
|
JNZ UCT_U4_PP
|
|
INC U4 4[EBX]
|
|
UCT_U4_PP:
|
|
MOV EBX,EAX
|
|
MOV EAX,U4 [EBX]
|
|
INC U4 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_U2_PP:
|
|
MOV EBX,EAX
|
|
MOVZX EAX,U2 [EBX]
|
|
INC U2 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_U1_PP:
|
|
MOV EBX,EAX
|
|
MOVZX EAX,U1 [EBX]
|
|
INC U1 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_U8_MM:
|
|
MOV EBX,EAX
|
|
MOV EAX,U4 [EBX]
|
|
MOV EDX,U4 4[EBX]
|
|
OR EAX,EAX
|
|
JNZ @@U8M
|
|
DEC U4 4[EBX]
|
|
@@U8M: DEC U4 [EBX]
|
|
UCT_U4_MM:
|
|
MOV EBX,EAX
|
|
MOV EAX,U4 [EBX]
|
|
DEC U4 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_U2_MM:
|
|
MOV EBX,EAX
|
|
MOVZX EAX,U2 [EBX]
|
|
DEC U2 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_U1_MM:
|
|
MOV EBX,EAX
|
|
MOVZX EAX,U1 [EBX]
|
|
DEC U1 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_PP_U8:
|
|
MOV EBX,EAX
|
|
INC U4 [EBX]
|
|
JNZ @@UP8
|
|
INC U4 4[EBX]
|
|
@@UP8: MOV EAX,U4 [EBX]
|
|
MOV EDX,U4 4[EBX]
|
|
UCT_PP_U4:
|
|
INC U4 [EAX]
|
|
MOV EAX,U4 [EAX]
|
|
XOR EDX,EDX
|
|
UCT_PP_U2:
|
|
INC U2 [EAX]
|
|
MOVZX EAX,U2 [EAX]
|
|
XOR EDX,EDX
|
|
UCT_PP_U1:
|
|
INC U1 [EAX]
|
|
MOVZX EAX,U1 [EAX]
|
|
XOR EDX,EDX
|
|
UCT_MM_U8:
|
|
MOV EBX,EAX
|
|
MOV EAX,U4 [EBX]
|
|
MOV EDX,U4 4[EBX]
|
|
OR EAX,EAX
|
|
JNZ @@UM8
|
|
DEC EDX
|
|
@@UM8: DEC EAX
|
|
MOV U4 [EBX],EAX
|
|
MOV U4 4[EBX],EDX
|
|
UCT_MM_U4:
|
|
DEC U4 [EAX]
|
|
MOV EAX,U4 [EAX]
|
|
XOR EDX,EDX
|
|
UCT_MM_U2:
|
|
DEC U2 [EAX]
|
|
MOVZX EAX,U2 [EAX]
|
|
XOR EDX,EDX
|
|
UCT_MM_U1:
|
|
DEC U1 [EAX]
|
|
MOVZX EAX,U1 [EAX]
|
|
XOR EDX,EDX
|
|
UCT_ESI_U4_PP:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,ESI
|
|
INC ESI
|
|
XOR EDX,EDX
|
|
UCT_ESI_U4_MM:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,ESI
|
|
DEC ESI
|
|
XOR EDX,EDX
|
|
UCT_ESI_PP_U4:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
INC ESI
|
|
MOV EAX,ESI
|
|
XOR EDX,EDX
|
|
UCT_ESI_MM_U4:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
DEC ESI
|
|
MOV EAX,ESI
|
|
XOR EDX,EDX
|
|
UCT_EDI_U4_PP:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,EDI
|
|
INC EDI
|
|
XOR EDX,EDX
|
|
UCT_EDI_U4_MM:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,EDI
|
|
DEC EDI
|
|
XOR EDX,EDX
|
|
UCT_EDI_PP_U4:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
INC EDI
|
|
MOV EAX,EDI
|
|
XOR EDX,EDX
|
|
UCT_EDI_MM_U4:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
DEC EDI
|
|
MOV EAX,EDI
|
|
XOR EDX,EDX
|
|
UCT_LEA_DISP32_EBP:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
LEA EAX,0x12345678[EBP]
|
|
UCT_LEA_DISP8_EBP:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
LEA EAX,0x12[EBP]
|
|
UCT_U8_DISP32_SCALED:
|
|
LEA EAX,U4 0x12345678[EAX*8]
|
|
MOV EDX,U4 4[EAX]
|
|
MOV EAX,U4 [EAX]
|
|
UCT_U4_DISP32_SCALED:
|
|
MOV EAX,U4 0x12345678[EAX*4]
|
|
XOR EDX,EDX
|
|
UCT_U2_DISP32_SCALED:
|
|
MOVZX EAX,U2 0x12345678[EAX*2]
|
|
XOR EDX,EDX
|
|
UCT_SHL:
|
|
MOV ECX,EAX
|
|
POP EAX
|
|
POP EDX
|
|
SUB ECX,32
|
|
JNC @@SL5
|
|
SHLD EDX,EAX
|
|
SHL EAX,CL
|
|
JMP UCT_SHR
|
|
@@SL5: MOV EDX,EAX
|
|
XOR EAX,EAX
|
|
SHL EDX,CL
|
|
UCT_SHR:
|
|
MOV ECX,EAX
|
|
POP EAX
|
|
POP EDX
|
|
SUB CL,32
|
|
JNC @@SR5
|
|
SHRD EAX,EDX
|
|
SHR EDX,CL
|
|
JMP UCT_SHL_CONSTANT1
|
|
@@SR5: MOV EAX,EDX
|
|
XOR EDX,EDX
|
|
SHR EAX,CL
|
|
UCT_SHL_CONSTANT1:
|
|
MOV CL,0x12
|
|
SHLD EDX,EAX
|
|
SHL EAX,CL
|
|
UCT_SHL_CONSTANT2:
|
|
MOV EDX,EAX
|
|
MOV CL,0x12
|
|
XOR EAX,EAX
|
|
SHL EDX,CL
|
|
UCT_SHR_CONSTANT1:
|
|
MOV CL,0x12
|
|
SHRD EAX,EDX
|
|
SHR EDX,CL
|
|
UCT_SHR_CONSTANT2:
|
|
MOV EAX,EDX
|
|
MOV CL,0x12
|
|
XOR EDX,EDX
|
|
SHR EAX,CL
|
|
UCT_POWER:
|
|
UCT_MULTIPLICATION:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MUL EBX
|
|
UCT_DIVISION:
|
|
MOV EBX,EAX
|
|
POP EAX
|
|
POP EDX
|
|
DIV EBX
|
|
XOR EDX,EDX
|
|
UCT_REMAINDER:
|
|
MOV EBX,EAX
|
|
POP EAX
|
|
POP EDX
|
|
DIV EBX
|
|
MOV EAX,EDX
|
|
XOR EDX,EDX
|
|
UCT_AND:
|
|
POP EBX
|
|
POP ECX
|
|
AND EAX,EBX
|
|
AND EDX,ECX
|
|
UCT_OR:
|
|
POP EBX
|
|
POP ECX
|
|
OR EAX,EBX
|
|
OR EDX,ECX
|
|
UCT_XOR:
|
|
POP EBX
|
|
POP ECX
|
|
XOR EAX,EBX
|
|
XOR EDX,ECX
|
|
UCT_ADDITION:
|
|
POP EBX
|
|
POP ECX
|
|
ADD EAX,EBX
|
|
ADC EDX,ECX
|
|
UCT_SUBTRACTION:
|
|
POP EBX
|
|
POP ECX
|
|
XCHG EAX,EBX
|
|
XCHG EDX,ECX
|
|
SUB EAX,EBX
|
|
SBB EDX,ECX
|
|
UCT_EQUAL_EQUAL:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EBX,EAX
|
|
SBB ECX,EDX
|
|
XOR EDX,EDX
|
|
XOR EAX,EAX
|
|
OR EBX,ECX
|
|
JNZ UCT_NOT_EQUAL_TO
|
|
INC EAX
|
|
UCT_NOT_EQUAL_TO:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EBX,EAX
|
|
SBB ECX,EDX
|
|
XOR EDX,EDX
|
|
XOR EAX,EAX
|
|
OR EBX,ECX
|
|
JZ UCT_LESS_THAN
|
|
INC EAX
|
|
UCT_LESS_THAN:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EBX,EAX
|
|
SBB ECX,EDX
|
|
MOV EAX,0
|
|
ADC EAX,0
|
|
XOR EDX,EDX
|
|
UCT_GREATER_THAN:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EAX,EBX
|
|
SBB EDX,ECX
|
|
MOV EAX,0
|
|
ADC EAX,0
|
|
XOR EDX,EDX
|
|
UCT_LESS_OR_EQUAL:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EAX,EBX
|
|
SBB EDX,ECX
|
|
MOV EAX,1
|
|
SBB EAX,0
|
|
XOR EDX,EDX
|
|
UCT_GREATER_OR_EQUAL:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EBX,EAX
|
|
SBB ECX,EDX
|
|
MOV EAX,1
|
|
SBB EAX,0
|
|
XOR EDX,EDX
|
|
UCT_AND_AND:
|
|
POP EBX
|
|
POP ECX
|
|
OR EAX,EDX
|
|
OR EBX,ECX
|
|
AND EAX,EAX
|
|
JZ @@AA2
|
|
XOR EAX,EAX
|
|
AND EBX,EBX
|
|
JZ @@AA2
|
|
INC EAX
|
|
@@AA2: XOR EDX,EDX
|
|
UCT_OR_OR:
|
|
POP EBX
|
|
POP ECX
|
|
OR EDX,ECX
|
|
OR EAX,EBX
|
|
OR EAX,EDX
|
|
JZ @@OO2
|
|
MOV EAX,1
|
|
@@OO2: XOR EDX,EDX
|
|
UCT_XOR_XOR:
|
|
POP EBX
|
|
POP ECX
|
|
OR EAX,EDX
|
|
JZ @@XX1
|
|
MOV EAX,1
|
|
@@XX1: OR EBX,ECX
|
|
JZ @@XX2
|
|
MOV EBX,1
|
|
@@XX2: XOR EAX,EBX
|
|
XOR EDX,EDX
|
|
UCT_COLON:
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
MOV EBX,12[EBP]
|
|
OR EBX,EBX
|
|
JZ @@C2
|
|
MOV EAX,4[EBP]
|
|
MOV EDX,8[EBP]
|
|
@@C2: POP EBP
|
|
ADD ESP,16
|
|
UCT_QUESTION:
|
|
UCT_ASSIGN_U8:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV U4 [EBX],EAX
|
|
MOV U4 4[EBX],EDX
|
|
UCT_ASSIGN_U4:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV U4 [EBX],EAX
|
|
UCT_ASSIGN_U2:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV U2 [EBX],AX
|
|
UCT_ASSIGN_U1:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV U1 [EBX],AL
|
|
UCT_SHL_EQUAL_U8:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV ECX,EAX
|
|
MOV EAX,U4 [EBX]
|
|
MOV EDX,U4 4[EBX]
|
|
SUB ECX,32
|
|
JNC @@SL6
|
|
SHLD EDX,EAX
|
|
SHL EAX,CL
|
|
JMP @@SL7
|
|
@@SL6: MOV EDX,EAX
|
|
XOR EAX,EAX
|
|
SHL EDX,CL
|
|
@@SL7: MOV U4 [EBX],EAX
|
|
MOV U4 4[EBX],EDX
|
|
UCT_SHL_EQUAL_U4:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV CL,AL
|
|
SHL U4 [EBX],CL
|
|
MOV EAX,U4 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_SHL_EQUAL_U2:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV CL,AL
|
|
SHL U2 [EBX],CL
|
|
MOVZX EAX,U2 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_SHL_EQUAL_U1:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV CL,AL
|
|
SHL U1 [EBX],CL
|
|
MOVZX EAX,U1 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_SHR_EQUAL_U8:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV ECX,EAX
|
|
MOV EAX,U4[EBX]
|
|
MOV EDX,U4 4[EBX]
|
|
SUB ECX,32
|
|
JNC @@SR8
|
|
SHRD EAX,EDX
|
|
SHR EDX,CL
|
|
JMP @@SR9
|
|
@@SR8: MOV EAX,EDX
|
|
XOR EDX,EDX
|
|
SHR EAX,CL
|
|
@@SR9: MOV U4 [EBX],EAX
|
|
MOV U4 4[EBX],EDX
|
|
UCT_SHR_EQUAL_U4:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV CL,AL
|
|
SHR U4 [EBX],CL
|
|
MOV EAX,U4 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_SHR_EQUAL_U2:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV CL,AL
|
|
SHR U2 [EBX],CL
|
|
MOVZX EAX,U2 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_SHR_EQUAL_U1:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV CL,AL
|
|
SHR U1 [EBX],CL
|
|
MOVZX EAX,U1 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_MUL_EQUAL_U8:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV EDX,U4 [EBX]
|
|
MUL EDX
|
|
MOV U4 [EBX],EAX
|
|
MOV U4 4[EBX],EDX
|
|
UCT_MUL_EQUAL_U4:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV EDX,U4 [EBX]
|
|
MUL EDX
|
|
MOV U4 [EBX],EAX
|
|
XOR EDX,EDX
|
|
UCT_MUL_EQUAL_U2:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOVZX EDX,U2 [EBX]
|
|
MUL EDX
|
|
MOV U2 [EBX],AX
|
|
MOVZX EAX,AX
|
|
XOR EDX,EDX
|
|
UCT_MUL_EQUAL_U1:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOVZX EDX,U1 [EBX]
|
|
MUL EDX
|
|
MOV U1 [EBX],AL
|
|
MOVZX EAX,AL
|
|
XOR EDX,EDX
|
|
UCT_DIV_EQUAL_U8:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV ECX,EAX
|
|
MOV EAX,U4 [EBX]
|
|
MOV EDX,U4 4[EBX]
|
|
DIV ECX
|
|
MOV U4 [EBX],EAX
|
|
XOR EDX,EDX
|
|
MOV U4 4[EBX],EDX
|
|
UCT_DIV_EQUAL_U4:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV ECX,EAX
|
|
MOV EAX,U4 [EBX]
|
|
XOR EDX,EDX
|
|
DIV ECX
|
|
MOV U4 [EBX],EAX
|
|
XOR EDX,EDX
|
|
UCT_DIV_EQUAL_U2:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV ECX,EAX
|
|
MOVZX EAX,U2 [EBX]
|
|
XOR EDX,EDX
|
|
DIV ECX
|
|
MOV U2 [EBX],AX
|
|
MOVZX EAX,AX
|
|
XOR EDX,EDX
|
|
UCT_DIV_EQUAL_U1:
|
|
POP EBX
|
|
ADD ESP,4
|
|
MOV ECX,EAX
|
|
MOVZX EAX,U1 [EBX]
|
|
XOR EDX,EDX
|
|
DIV ECX
|
|
MOV U1 [EBX],AL
|
|
MOVZX EAX,AL
|
|
XOR EDX,EDX
|
|
UCT_AND_EQUAL_U8:
|
|
POP EBX
|
|
ADD ESP,4
|
|
AND U4 [EBX],EAX
|
|
MOV EAX,U4 [EBX]
|
|
AND U4 4[EBX],EDX
|
|
MOV EDX,U4 4[EBX]
|
|
UCT_AND_EQUAL_U4:
|
|
POP EBX
|
|
ADD ESP,4
|
|
AND U4 [EBX],EAX
|
|
MOV EAX,U4 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_AND_EQUAL_U2:
|
|
POP EBX
|
|
ADD ESP,4
|
|
AND U2 [EBX],AX
|
|
MOVZX EAX,U2 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_AND_EQUAL_U1:
|
|
POP EBX
|
|
ADD ESP,4
|
|
AND U1 [EBX],AL
|
|
MOVZX EAX,U1 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_OR_EQUAL_U8:
|
|
POP EBX
|
|
ADD ESP,4
|
|
OR U4 [EBX],EAX
|
|
MOV EAX,U4 [EBX]
|
|
OR U4 4[EBX],EDX
|
|
MOV EDX,U4 4[EBX]
|
|
UCT_OR_EQUAL_U4:
|
|
POP EBX
|
|
ADD ESP,4
|
|
OR U4 [EBX],EAX
|
|
MOV EAX,U4 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_OR_EQUAL_U2:
|
|
POP EBX
|
|
ADD ESP,4
|
|
OR U2 [EBX],AX
|
|
MOVZX EAX,U2 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_OR_EQUAL_U1:
|
|
POP EBX
|
|
ADD ESP,4
|
|
OR U1 [EBX],AL
|
|
MOVZX EAX,U1 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_XOR_EQUAL_U8:
|
|
POP EBX
|
|
ADD ESP,4
|
|
XOR U4 [EBX],EAX
|
|
MOV EAX,U4 [EBX]
|
|
XOR U4 4[EBX],EDX
|
|
MOV EDX,U4 4[EBX]
|
|
UCT_XOR_EQUAL_U4:
|
|
POP EBX
|
|
ADD ESP,4
|
|
XOR U4 [EBX],EAX
|
|
MOV EAX,U4 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_XOR_EQUAL_U2:
|
|
POP EBX
|
|
ADD ESP,4
|
|
XOR U2 [EBX],AX
|
|
MOVZX EAX,U2 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_XOR_EQUAL_U1:
|
|
POP EBX
|
|
ADD ESP,4
|
|
XOR U1 [EBX],AL
|
|
MOVZX EAX,U1 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_ADD_EQUAL_U8:
|
|
POP EBX
|
|
ADD ESP,4
|
|
ADD U4 [EBX],EAX
|
|
MOV EAX,U4 [EBX]
|
|
ADC U4 4[EBX],EDX
|
|
MOV EDX,U4 4[EBX]
|
|
UCT_ADD_EQUAL_U4:
|
|
POP EBX
|
|
ADD ESP,4
|
|
ADD U4 [EBX],EAX
|
|
MOV EAX,U4 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_ADD_EQUAL_U2:
|
|
POP EBX
|
|
ADD ESP,4
|
|
ADD U2 [EBX],AX
|
|
MOVZX EAX,U2 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_ADD_EQUAL_U1:
|
|
POP EBX
|
|
ADD ESP,4
|
|
ADD U1 [EBX],AL
|
|
MOVZX EAX,U1 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_SUB_EQUAL_U8:
|
|
POP EBX
|
|
ADD ESP,4
|
|
SUB U4 [EBX],EAX
|
|
MOV EAX,U4 [EBX]
|
|
SBB U4 4[EBX],EDX
|
|
MOV EDX,U4 4[EBX]
|
|
UCT_SUB_EQUAL_U4:
|
|
POP EBX
|
|
ADD ESP,4
|
|
SUB U4 [EBX],EAX
|
|
MOV EAX,U4 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_SUB_EQUAL_U2:
|
|
POP EBX
|
|
ADD ESP,4
|
|
SUB U2 [EBX],AX
|
|
MOVZX EAX,U2 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_SUB_EQUAL_U1:
|
|
POP EBX
|
|
ADD ESP,4
|
|
SUB U1 [EBX],AL
|
|
MOVZX EAX,U1 [EBX]
|
|
XOR EDX,EDX
|
|
UCT_ESI_ASSIGN_U4:
|
|
MOV ESI,EAX
|
|
UCT_ESI_SHL_EQUAL_U4:
|
|
MOV ECX,EAX
|
|
SHL ESI,CL
|
|
MOV EAX,ESI
|
|
XOR EDX,EDX
|
|
UCT_ESI_SHR_EQUAL_U4:
|
|
MOV ECX,EAX
|
|
SHR ESI,CL
|
|
MOV EAX,ESI
|
|
XOR EDX,EDX
|
|
UCT_ESI_MUL_EQUAL_U4:
|
|
MOV EDX,ESI
|
|
MUL EDX
|
|
MOV ESI,EAX
|
|
XOR EDX,EDX
|
|
UCT_ESI_DIV_EQUAL_U4:
|
|
MOV ECX,EAX
|
|
MOV EAX,ESI
|
|
XOR EDX,EDX
|
|
DIV ECX
|
|
MOV ESI,EAX
|
|
XOR EDX,EDX
|
|
UCT_ESI_AND_EQUAL_U4:
|
|
AND ESI,EAX
|
|
MOV EAX,ESI
|
|
XOR EDX,EDX
|
|
UCT_ESI_OR_EQUAL_U4:
|
|
OR ESI,EAX
|
|
MOV EAX,ESI
|
|
XOR EDX,EDX
|
|
UCT_ESI_XOR_EQUAL_U4:
|
|
XOR ESI,EAX
|
|
MOV EAX,ESI
|
|
XOR EDX,EDX
|
|
UCT_ESI_ADD_EQUAL_U4:
|
|
ADD ESI,EAX
|
|
MOV EAX,ESI
|
|
XOR EDX,EDX
|
|
UCT_ESI_SUB_EQUAL_U4:
|
|
SUB ESI,EAX
|
|
MOV EAX,ESI
|
|
XOR EDX,EDX
|
|
UCT_EDI_ASSIGN_U4:
|
|
MOV EDI,EAX
|
|
UCT_EDI_SHL_EQUAL_U4:
|
|
MOV ECX,EAX
|
|
SHL EDI,CL
|
|
MOV EAX,EDI
|
|
XOR EDX,EDX
|
|
UCT_EDI_SHR_EQUAL_U4:
|
|
MOV ECX,EAX
|
|
SHR EDI,CL
|
|
MOV EAX,EDI
|
|
XOR EDX,EDX
|
|
UCT_EDI_MUL_EQUAL_U4:
|
|
MOV EDX,EDI
|
|
MUL EDX
|
|
MOV EDI,EAX
|
|
XOR EDX,EDX
|
|
UCT_EDI_DIV_EQUAL_U4:
|
|
MOV ECX,EAX
|
|
MOV EAX,EDI
|
|
XOR EDX,EDX
|
|
DIV ECX
|
|
MOV EDI,EAX
|
|
XOR EDX,EDX
|
|
UCT_EDI_AND_EQUAL_U4:
|
|
AND EDI,EAX
|
|
MOV EAX,EDI
|
|
XOR EDX,EDX
|
|
UCT_EDI_OR_EQUAL_U4:
|
|
OR EDI,EAX
|
|
MOV EAX,EDI
|
|
XOR EDX,EDX
|
|
UCT_EDI_XOR_EQUAL_U4:
|
|
XOR EDI,EAX
|
|
MOV EAX,EDI
|
|
XOR EDX,EDX
|
|
UCT_EDI_ADD_EQUAL_U4:
|
|
ADD EDI,EAX
|
|
MOV EAX,EDI
|
|
XOR EDX,EDX
|
|
UCT_EDI_SUB_EQUAL_U4:
|
|
SUB EDI,EAX
|
|
MOV EAX,EDI
|
|
XOR EDX,EDX
|
|
UCT_ADD64:
|
|
ADD EAX,0x12345678
|
|
ADC EDX,0 //TODO
|
|
UCT_ADD32:
|
|
ADD EAX,0x12345678
|
|
ADC EDX,0
|
|
UCT_ADD8:
|
|
ADD EAX,0x12
|
|
ADC EDX,0
|
|
UCT_INC:
|
|
INC EAX
|
|
JNZ UCT_SUB64
|
|
INC EDX
|
|
UCT_SUB64:
|
|
SUB EAX,0x12345678
|
|
SBB EDX,0 //TODO
|
|
UCT_SUB32:
|
|
SUB EAX,0x12345678
|
|
SBB EDX,0
|
|
UCT_SUB8:
|
|
SUB EAX,0x12
|
|
SBB EDX,0
|
|
UCT_DEC:
|
|
OR EAX,EAX
|
|
JNZ @@UD2
|
|
DEC EDX
|
|
@@UD2: DEC EAX
|
|
UCT_ENTER:
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
SUB ESP,0x012345678
|
|
UCT_LEAVE:
|
|
ADD ESP,0x012345678
|
|
POP EBP
|
|
RET
|
|
UCT_ENTER1:
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
SUB ESP,0x012345678
|
|
PUSH ESI
|
|
MOV ESI,U4 0x12345678[EBP]
|
|
UCT_LEAVE1:
|
|
POP ESI
|
|
ADD ESP,0x012345678
|
|
POP EBP
|
|
RET
|
|
UCT_ENTER2:
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
SUB ESP,0x012345678
|
|
PUSH ESI
|
|
PUSH EDI
|
|
MOV ESI,U4 0x12345678[EBP]
|
|
MOV EDI,U4 0x12345678[EBP]
|
|
UCT_LEAVE2:
|
|
POP EDI
|
|
POP ESI
|
|
ADD ESP,0x012345678
|
|
POP EBP
|
|
RET
|
|
UCT_ADD_ESP32:
|
|
ADD ESP,0x12345678
|
|
UCT_ADD_ESP8:
|
|
ADD ESP,0x12
|
|
UCT_RET:
|
|
RET
|
|
UCT_CALL:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
CALL UCT_CALL
|
|
UCT_CALL_INDIRECT:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,ESP
|
|
CALL U4 0x12345678[EAX]
|
|
UCT_CALL_INDIRECT2:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
CALL U4 [0x12345678]
|
|
UCT_IRQ:
|
|
INT I_COUT //Gets patched
|
|
UCT_CLI:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
CLI
|
|
UCT_STI:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
STI
|
|
UCT_GET_FLAGS:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSHFD
|
|
POP EAX
|
|
XOR EDX,EDX
|
|
UCT_SET_FLAGS:
|
|
PUSH EAX
|
|
POPFD
|
|
UCT_GET_BASE_PTR:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,EBP
|
|
XOR EDX,EDX
|
|
UCT_SET_BASE_PTR:
|
|
MOV EBP,EAX
|
|
UCT_GET_STACK_PTR:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EAX,ESP
|
|
XOR EDX,EDX
|
|
UCT_SET_STACK_PTR:
|
|
MOV ESP,EAX
|
|
UCT_GET_LABEL:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOV EAX,0x12345678
|
|
UCT_ABSOLUTE_ADDRESS:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOV EAX,0x12345678
|
|
UCT_LABEL:
|
|
UCT_TYPE:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
MOV EAX,0x12345678
|
|
UCT_BT:
|
|
MOV EBX,EAX
|
|
POP EDX
|
|
ADD ESP,4
|
|
XOR EAX,EAX
|
|
BT U4 [EBX],EDX
|
|
ADC EAX,0
|
|
XOR EDX,EDX
|
|
UCT_BTS:
|
|
MOV EBX,EAX
|
|
POP EDX
|
|
ADD ESP,4
|
|
XOR EAX,EAX
|
|
BTS U4 [EBX],EDX
|
|
ADC EAX,0
|
|
XOR EDX,EDX
|
|
UCT_BTR:
|
|
MOV EBX,EAX
|
|
POP EDX
|
|
ADD ESP,4
|
|
XOR EAX,EAX
|
|
BTR U4 [EBX],EDX
|
|
ADC EAX,0
|
|
XOR EDX,EDX
|
|
UCT_BTC:
|
|
MOV EBX,EAX
|
|
POP EDX
|
|
ADD ESP,4
|
|
XOR EAX,EAX
|
|
BTC U4 [EBX],EDX
|
|
ADC EAX,0
|
|
XOR EDX,EDX
|
|
UCT_BSF:
|
|
BSF EAX,EAX
|
|
JNZ @@BSF1
|
|
NOT EAX
|
|
@@BSF1: CDQ
|
|
UCT_BSR:
|
|
BSR EAX,EAX
|
|
JNZ @@BSR1
|
|
NOT EAX
|
|
@@BSR1: CDQ
|
|
UCT_INSQUE:
|
|
POP EDX
|
|
ADD ESP,4
|
|
MOV EBX,[EDX]
|
|
MOV [EDX],EAX
|
|
MOV [EAX],EBX
|
|
MOV 4[EAX],EDX
|
|
MOV 4[EBX],EAX
|
|
UCT_INSQUE_REV:
|
|
POP EDX
|
|
ADD ESP,4
|
|
MOV EBX,4[EDX]
|
|
MOV [EBX],EAX
|
|
MOV [EAX],EDX
|
|
MOV 4[EAX],EBX
|
|
MOV 4[EDX],EAX
|
|
UCT_REMQUE:
|
|
MOV EBX,[EAX]
|
|
MOV EDX,4[EAX]
|
|
MOV [EDX],EBX
|
|
MOV 4[EBX],EDX
|
|
UCT_STRLEN:
|
|
MOV EDX,EAX
|
|
@@SL3: MOV BL,U1 [EAX]
|
|
INC EAX
|
|
OR BL,BL
|
|
JNZ @@SL3
|
|
SUB EAX,EDX
|
|
DEC EAX
|
|
XOR EDX,EDX
|
|
UCT_MEMCPY:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
PUSH ESI
|
|
PUSH EDI
|
|
MOV EDI,4[EBP]
|
|
MOV ESI,12[EBP]
|
|
MOV ECX,20[EBP]
|
|
OR ECX,ECX
|
|
JZ @@1
|
|
REP_MOVSB
|
|
@@1: POP EDI
|
|
POP ESI
|
|
POP EBP
|
|
ADD ESP,24
|
|
UCT_MEMSET:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
PUSH EDI
|
|
MOV EDI,4[EBP]
|
|
MOV ECX,20[EBP]
|
|
MOV EAX,12[EBP]
|
|
OR ECX,ECX
|
|
JZ @@2
|
|
REP_STOSB
|
|
@@2: POP EDI
|
|
POP EBP
|
|
ADD ESP,24
|
|
UCT_INPD:
|
|
MOV EDX,EAX
|
|
IN EAX,DX
|
|
XOR EDX,EDX
|
|
UCT_INPW:
|
|
MOV EDX,EAX
|
|
XOR EAX,EAX
|
|
IN AX,DX
|
|
XOR EDX,EDX
|
|
UCT_INP:
|
|
MOV EDX,EAX
|
|
XOR EAX,EAX
|
|
IN AL,DX
|
|
XOR EDX,EDX
|
|
UCT_OUTPD:
|
|
MOV EDX,EAX
|
|
POP EAX
|
|
ADD ESP,4
|
|
OUT DX,EAX
|
|
UCT_OUTPW:
|
|
MOV EDX,EAX
|
|
POP EAX
|
|
ADD ESP,4
|
|
OUT DX,AX
|
|
UCT_OUTP:
|
|
MOV EDX,EAX
|
|
POP EAX
|
|
ADD ESP,4
|
|
OUT DX,AL
|
|
UCT_JMP:
|
|
JMP U4 FAR_AWAY
|
|
UCT_SHORT_JMP:
|
|
JMP UCT_SHORT_JMP
|
|
UCT_SWITCH:
|
|
POP EBX
|
|
ADD ESP,12
|
|
CMP EBX,EAX
|
|
JAE UCT_SKIPZ
|
|
JMP U4 0x12345678[EBX*4]
|
|
UCT_SKIPZ:
|
|
OR EAX,EDX
|
|
JZ UCT_SKIPZ
|
|
UCT_SKIPZ2:
|
|
OR EAX,EDX
|
|
JNZ UCT_SKIPNZ
|
|
JMP U4 FAR_AWAY
|
|
UCT_SKIPNZ:
|
|
OR EAX,EDX
|
|
JNZ UCT_SKIPNZ
|
|
UCT_SKIPNZ2:
|
|
OR EAX,EDX
|
|
JZ UCT_EQUAL_EQUAL_SKIPZ
|
|
JMP U4 FAR_AWAY
|
|
UCT_EQUAL_EQUAL_SKIPZ:
|
|
POP EBX
|
|
POP ECX
|
|
CMP ECX,EDX
|
|
JNE @@EE2B
|
|
CMP EBX,EAX
|
|
@@EE2B: JNE UCT_EQUAL_EQUAL_SKIPZ
|
|
UCT_EQUAL_EQUAL_SKIPZ2:
|
|
POP EBX
|
|
POP ECX
|
|
CMP ECX,EDX
|
|
JNE @@EE2C
|
|
CMP EBX,EAX
|
|
@@EE2C: JNE U4 FAR_AWAY
|
|
UCT_NOT_EQUAL_TO_SKIPZ:
|
|
POP EBX
|
|
POP ECX
|
|
CMP ECX,EDX
|
|
JNE @@NE2B
|
|
CMP EBX,EAX
|
|
@@NE2B: JE UCT_NOT_EQUAL_TO_SKIPZ
|
|
UCT_NOT_EQUAL_TO_SKIPZ2:
|
|
POP EBX
|
|
POP ECX
|
|
CMP ECX,EDX
|
|
JNE @@NE2C
|
|
CMP EBX,EAX
|
|
@@NE2C: JE U4 FAR_AWAY
|
|
UCT_LESS_THAN_SKIPZ:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EBX,EAX
|
|
SBB ECX,EDX
|
|
JNC UCT_LESS_THAN_SKIPZ
|
|
UCT_LESS_THAN_SKIPZ2:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EBX,EAX
|
|
SBB ECX,EDX
|
|
JNC U4 FAR_AWAY
|
|
UCT_GREATER_THAN_SKIPZ:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EAX,EBX
|
|
SBB EDX,ECX
|
|
JNC UCT_GREATER_THAN_SKIPZ
|
|
UCT_GREATER_THAN_SKIPZ2:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EAX,EBX
|
|
SBB EDX,ECX
|
|
JNC U4 FAR_AWAY
|
|
UCT_LESS_OR_EQUAL_SKIPZ:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EAX,EBX
|
|
SBB EDX,ECX
|
|
JC UCT_LESS_OR_EQUAL_SKIPZ
|
|
UCT_LESS_OR_EQUAL_SKIPZ2:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EAX,EBX
|
|
SBB EDX,ECX
|
|
JC U4 FAR_AWAY
|
|
UCT_GREATER_OR_EQUAL_SKIPZ:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EBX,EAX
|
|
SBB ECX,EDX
|
|
JC UCT_GREATER_OR_EQUAL_SKIPZ
|
|
UCT_GREATER_OR_EQUAL_SKIPZ2:
|
|
POP EBX
|
|
POP ECX
|
|
SUB EBX,EAX
|
|
SBB ECX,EDX
|
|
JC U4 FAR_AWAY
|
|
UCT_AND_AND_SKIPZ:
|
|
POP EBX
|
|
POP ECX
|
|
OR EAX,EDX
|
|
JZ @@AAZ1
|
|
OR EBX,ECX
|
|
@@AAZ1: JZ UCT_AND_AND_SKIPZ
|
|
UCT_AND_AND_SKIPZ2:
|
|
POP EBX
|
|
POP ECX
|
|
OR EAX,EDX
|
|
JZ @@AAZ2
|
|
OR EBX,ECX
|
|
@@AAZ2: JZ U4 FAR_AWAY
|
|
UCT_AND_AND_SKIPNZ:
|
|
POP EBX
|
|
POP ECX
|
|
OR EAX,EDX
|
|
JZ UCT_AND_AND_SKIPNZ2
|
|
OR EBX,ECX
|
|
JNZ UCT_AND_AND_SKIPNZ
|
|
UCT_AND_AND_SKIPNZ2:
|
|
POP EBX
|
|
POP ECX
|
|
OR EAX,EDX
|
|
JZ UCT_OR_OR_SKIPZ
|
|
OR EBX,ECX
|
|
JNZ U4 FAR_AWAY
|
|
UCT_OR_OR_SKIPZ:
|
|
POP EBX
|
|
POP ECX
|
|
OR EAX,EDX
|
|
OR EBX,ECX
|
|
OR EAX,EBX
|
|
JZ UCT_OR_OR_SKIPZ
|
|
UCT_OR_OR_SKIPZ2:
|
|
POP EBX
|
|
POP ECX
|
|
OR EAX,EDX
|
|
OR EBX,ECX
|
|
OR EAX,EBX
|
|
JZ U4 FAR_AWAY
|
|
UCT_OR_OR_SKIPNZ:
|
|
POP EBX
|
|
POP ECX
|
|
OR EAX,EDX
|
|
OR EBX,ECX
|
|
OR EAX,EBX
|
|
JNZ UCT_OR_OR_SKIPNZ
|
|
UCT_OR_OR_SKIPNZ2:
|
|
POP EBX
|
|
POP ECX
|
|
OR EAX,EDX
|
|
OR EBX,ECX
|
|
OR EAX,EBX
|
|
JNZ U4 FAR_AWAY
|
|
UCT_LEA_DISP32_ESI:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
LEA EAX,0x12345678[ESI]
|
|
UCT_LEA_DISP8_ESI:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
LEA EAX,0x12[ESI]
|
|
UCT_LEA_DISP32_EDI:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
LEA EAX,0x12345678[EDI]
|
|
UCT_LEA_DISP8_EDI:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
XOR EDX,EDX
|
|
LEA EAX,0x12[EDI]
|
|
UCT_PUSH_U8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH U4 0x12345678
|
|
PUSH U4 0x9ABCDEF0
|
|
UCT_PUSH_U4:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH 0
|
|
PUSH U4 0x9ABCDEF0
|
|
UCT_PUSH_U2:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH 0
|
|
PUSH U4 0x9ABCDEF0
|
|
UCT_PUSH_U1:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH 0
|
|
PUSH 0x12
|
|
UCT_PUSH_NEG_U4:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH -1
|
|
PUSH U4 0x9ABCDEF0
|
|
UCT_PUSH_NEG_U2:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH -1
|
|
PUSH U4 0x9ABCDEF0
|
|
UCT_PUSH_NEG_U1:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH -1
|
|
PUSH 0x12
|
|
UCT_PUSH_DOUBLE:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH U4 0x12345678
|
|
PUSH U4 0x9ABCDEF0
|
|
UCT_PUSH_U8_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
LEA EAX,U4 0x12345678[EBP]
|
|
PUSH U4 4[EAX]
|
|
PUSH U4 [EAX]
|
|
UCT_PUSH_U8_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
LEA EAX,U4 0x12[EBP]
|
|
PUSH U4 4[EAX]
|
|
PUSH U4 [EAX]
|
|
UCT_PUSH_ESI_U8_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
LEA EAX,U4 0x12345678[ESI]
|
|
PUSH U4 4[EAX]
|
|
PUSH U4 [EAX]
|
|
UCT_PUSH_ESI_U8_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
LEA EAX,U4 0x12[ESI]
|
|
PUSH U4 4[EAX]
|
|
PUSH U4 [EAX]
|
|
UCT_PUSH_EDI_U8_DISP32:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
LEA EAX,U4 0x12345678[EDI]
|
|
PUSH U4 4[EAX]
|
|
PUSH U4 [EAX]
|
|
UCT_PUSH_EDI_U8_DISP8:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
LEA EAX,U4 0x12[EDI]
|
|
PUSH U4 4[EAX]
|
|
PUSH U4 [EAX]
|
|
UCT_PUSH_DEREF_U8:
|
|
PUSH U4 4[EAX]
|
|
PUSH U4 [EAX]
|
|
UCT_PUSH_U8_DISP32_SCALED:
|
|
LEA EAX,U4 0x12345678[EAX*8]
|
|
PUSH U4 4[EAX]
|
|
PUSH U4 [EAX]
|
|
UCT_BT_CONSTANT:
|
|
MOV EBX,EAX
|
|
XOR EAX,EAX
|
|
BT U4 [EBX],0x12
|
|
ADC EAX,0
|
|
XOR EDX,EDX
|
|
UCT_BTS_CONSTANT:
|
|
MOV EBX,EAX
|
|
XOR EAX,EAX
|
|
BTS U4 [EBX],0x12
|
|
ADC EAX,0
|
|
XOR EDX,EDX
|
|
UCT_BTR_CONSTANT:
|
|
MOV EBX,EAX
|
|
XOR EAX,EAX
|
|
BTR U4 [EBX],0x12
|
|
ADC EAX,0
|
|
XOR EDX,EDX
|
|
UCT_BTC_CONSTANT:
|
|
MOV EBX,EAX
|
|
XOR EAX,EAX
|
|
BTC U4 [EBX],0x12
|
|
ADC EAX,0
|
|
XOR EDX,EDX
|
|
UCT_ESI_NEXT_EQUAL_U4:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV ESI,U4 [ESI]
|
|
MOV EAX,ESI
|
|
XOR EDX,EDX
|
|
UCT_EDI_NEXT_EQUAL_U4:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
MOV EDI,U4 [EDI]
|
|
MOV EAX,EDI
|
|
XOR EDX,EDX
|
|
UCT_ADD_EQUAL_U8_CONSTANT_U1:
|
|
MOV EBX,EAX
|
|
ADD U4 [EBX],0x12
|
|
ADC U4 4[EBX],0
|
|
MOV EAX,U4 [EBX]
|
|
MOV EDX,U4 4[EBX]
|
|
UCT_SUB_EQUAL_U8_CONSTANT_U1:
|
|
MOV EBX,EAX
|
|
SUB U4 [EBX],0x12
|
|
SBB U4 4[EBX],0
|
|
MOV EAX,U4 [EBX]
|
|
MOV EDX,U4 4[EBX]
|
|
UCT_ADD_EQUAL_U4_CONSTANT_U1:
|
|
ADD U4 [EAX],0x12
|
|
MOV EAX,U4 [EAX]
|
|
XOR EDX,EDX
|
|
UCT_ESI_ADD_EQUAL_U4_CONSTANT_U1:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
ADD ESI,0x12
|
|
MOV EAX,ESI
|
|
XOR EDX,EDX
|
|
UCT_EDI_ADD_EQUAL_U4_CONSTANT_U1:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
ADD EDI,0x12
|
|
MOV EAX,EDI
|
|
XOR EDX,EDX
|
|
UCT_TABLE_END:
|
|
ALIGN 8,0x90
|
|
DOUBLE_CODE_TABLE::
|
|
DU4 DCT_NULL;
|
|
DU4 DCT_NOP;
|
|
DU4 DCT_END_EXP;
|
|
DU4 DCT_ZERO;
|
|
DU4 DCT_U8;
|
|
DU4 DCT_U4;
|
|
DU4 DCT_U2;
|
|
DU4 DCT_U1;
|
|
DU4 DCT_DOUBLE;
|
|
DU4 DCT_STRING_CONSTANT;
|
|
DU4 DCT_EBP;
|
|
DU4 DCT_FS;
|
|
DU4 DCT_ESI;
|
|
DU4 DCT_EDI;
|
|
DU4 DCT_TO_DOUBLE;
|
|
DU4 DCT_TO_INT;
|
|
DU4 DCT_COM;
|
|
DU4 DCT_NOT;
|
|
DU4 DCT_UNARY_MINUS;
|
|
DU4 DCT_ADDRESS;
|
|
DU4 DCT_U8_DISP32;
|
|
DU4 DCT_U4_DISP32;
|
|
DU4 DCT_U2_DISP32;
|
|
DU4 DCT_U1_DISP32;
|
|
DU4 DCT_U8_DISP8;
|
|
DU4 DCT_U4_DISP8;
|
|
DU4 DCT_U2_DISP8;
|
|
DU4 DCT_U1_DISP8;
|
|
DU4 DCT_FS_U8_DISP32;
|
|
DU4 DCT_FS_U4_DISP32;
|
|
DU4 DCT_FS_U2_DISP32;
|
|
DU4 DCT_FS_U1_DISP32;
|
|
DU4 DCT_ESI_U8_DISP32;
|
|
DU4 DCT_ESI_U4_DISP32;
|
|
DU4 DCT_ESI_U2_DISP32;
|
|
DU4 DCT_ESI_U1_DISP32;
|
|
DU4 DCT_ESI_U8_DISP8;
|
|
DU4 DCT_ESI_U4_DISP8;
|
|
DU4 DCT_ESI_U2_DISP8;
|
|
DU4 DCT_ESI_U1_DISP8;
|
|
DU4 DCT_EDI_U8_DISP32;
|
|
DU4 DCT_EDI_U4_DISP32;
|
|
DU4 DCT_EDI_U2_DISP32;
|
|
DU4 DCT_EDI_U1_DISP32;
|
|
DU4 DCT_EDI_U8_DISP8;
|
|
DU4 DCT_EDI_U4_DISP8;
|
|
DU4 DCT_EDI_U2_DISP8;
|
|
DU4 DCT_EDI_U1_DISP8;
|
|
DU4 DCT_DEREF_U8;
|
|
DU4 DCT_DEREF_U4;
|
|
DU4 DCT_DEREF_U2;
|
|
DU4 DCT_DEREF_U1;
|
|
DU4 DCT_ESI_DEREF_U8;
|
|
DU4 DCT_ESI_DEREF_U4;
|
|
DU4 DCT_ESI_DEREF_U2;
|
|
DU4 DCT_ESI_DEREF_U1;
|
|
DU4 DCT_EDI_DEREF_U8;
|
|
DU4 DCT_EDI_DEREF_U4;
|
|
DU4 DCT_EDI_DEREF_U2;
|
|
DU4 DCT_EDI_DEREF_U1;
|
|
DU4 DCT_U8_PP;
|
|
DU4 DCT_U4_PP;
|
|
DU4 DCT_U2_PP;
|
|
DU4 DCT_U1_PP;
|
|
DU4 DCT_U8_MM;
|
|
DU4 DCT_U4_MM;
|
|
DU4 DCT_U2_MM;
|
|
DU4 DCT_U1_MM;
|
|
DU4 DCT_PP_U8;
|
|
DU4 DCT_PP_U4;
|
|
DU4 DCT_PP_U2;
|
|
DU4 DCT_PP_U1;
|
|
DU4 DCT_MM_U8;
|
|
DU4 DCT_MM_U4;
|
|
DU4 DCT_MM_U2;
|
|
DU4 DCT_MM_U1;
|
|
DU4 DCT_ESI_U4_PP;
|
|
DU4 DCT_ESI_U4_MM;
|
|
DU4 DCT_ESI_PP_U4;
|
|
DU4 DCT_ESI_MM_U4;
|
|
DU4 DCT_EDI_U4_PP;
|
|
DU4 DCT_EDI_U4_MM;
|
|
DU4 DCT_EDI_PP_U4;
|
|
DU4 DCT_EDI_MM_U4;
|
|
DU4 DCT_LEA_DISP32_EBP;
|
|
DU4 DCT_LEA_DISP8_EBP;
|
|
DU4 DCT_U8_DISP32_SCALED;
|
|
DU4 DCT_U4_DISP32_SCALED;
|
|
DU4 DCT_U2_DISP32_SCALED;
|
|
DU4 DCT_SHL;
|
|
DU4 DCT_SHR;
|
|
DU4 DCT_SHL_CONSTANT1;
|
|
DU4 DCT_SHL_CONSTANT2;
|
|
DU4 DCT_SHR_CONSTANT1;
|
|
DU4 DCT_SHR_CONSTANT2;
|
|
DU4 DCT_POWER;
|
|
DU4 DCT_MULTIPLICATION;
|
|
DU4 DCT_DIVISION;
|
|
DU4 DCT_REMAINDER;
|
|
DU4 DCT_AND;
|
|
DU4 DCT_OR;
|
|
DU4 DCT_XOR;
|
|
DU4 DCT_ADDITION;
|
|
DU4 DCT_SUBTRACTION;
|
|
DU4 DCT_EQUAL_EQUAL;
|
|
DU4 DCT_NOT_EQUAL_TO;
|
|
DU4 DCT_LESS_THAN;
|
|
DU4 DCT_GREATER_THAN;
|
|
DU4 DCT_LESS_OR_EQUAL;
|
|
DU4 DCT_GREATER_OR_EQUAL;
|
|
DU4 DCT_AND_AND;
|
|
DU4 DCT_OR_OR;
|
|
DU4 DCT_XOR_XOR;
|
|
DU4 DCT_COLON;
|
|
DU4 DCT_QUESTION;
|
|
DU4 DCT_ASSIGN_U8;
|
|
DU4 DCT_ASSIGN_U4;
|
|
DU4 DCT_ASSIGN_U2;
|
|
DU4 DCT_ASSIGN_U1;
|
|
DU4 DCT_SHL_EQUAL_U8;
|
|
DU4 DCT_SHL_EQUAL_U4;
|
|
DU4 DCT_SHL_EQUAL_U2;
|
|
DU4 DCT_SHL_EQUAL_U1;
|
|
DU4 DCT_SHR_EQUAL_U8;
|
|
DU4 DCT_SHR_EQUAL_U4;
|
|
DU4 DCT_SHR_EQUAL_U2;
|
|
DU4 DCT_SHR_EQUAL_U1;
|
|
DU4 DCT_MUL_EQUAL_U8;
|
|
DU4 DCT_MUL_EQUAL_U4;
|
|
DU4 DCT_MUL_EQUAL_U2;
|
|
DU4 DCT_MUL_EQUAL_U1;
|
|
DU4 DCT_DIV_EQUAL_U8;
|
|
DU4 DCT_DIV_EQUAL_U4;
|
|
DU4 DCT_DIV_EQUAL_U2;
|
|
DU4 DCT_DIV_EQUAL_U1;
|
|
DU4 DCT_AND_EQUAL_U8;
|
|
DU4 DCT_AND_EQUAL_U4;
|
|
DU4 DCT_AND_EQUAL_U2;
|
|
DU4 DCT_AND_EQUAL_U1;
|
|
DU4 DCT_OR_EQUAL_U8;
|
|
DU4 DCT_OR_EQUAL_U4;
|
|
DU4 DCT_OR_EQUAL_U2;
|
|
DU4 DCT_OR_EQUAL_U1;
|
|
DU4 DCT_XOR_EQUAL_U8;
|
|
DU4 DCT_XOR_EQUAL_U4;
|
|
DU4 DCT_XOR_EQUAL_U2;
|
|
DU4 DCT_XOR_EQUAL_U1;
|
|
DU4 DCT_ADD_EQUAL_U8;
|
|
DU4 DCT_ADD_EQUAL_U4;
|
|
DU4 DCT_ADD_EQUAL_U2;
|
|
DU4 DCT_ADD_EQUAL_U1;
|
|
DU4 DCT_SUB_EQUAL_U8;
|
|
DU4 DCT_SUB_EQUAL_U4;
|
|
DU4 DCT_SUB_EQUAL_U2;
|
|
DU4 DCT_SUB_EQUAL_U1;
|
|
DU4 DCT_ESI_ASSIGN_U4;
|
|
DU4 DCT_ESI_SHL_EQUAL_U4;
|
|
DU4 DCT_ESI_SHR_EQUAL_U4;
|
|
DU4 DCT_ESI_MUL_EQUAL_U4;
|
|
DU4 DCT_ESI_DIV_EQUAL_U4;
|
|
DU4 DCT_ESI_AND_EQUAL_U4;
|
|
DU4 DCT_ESI_OR_EQUAL_U4;
|
|
DU4 DCT_ESI_XOR_EQUAL_U4;
|
|
DU4 DCT_ESI_ADD_EQUAL_U4;
|
|
DU4 DCT_ESI_SUB_EQUAL_U4;
|
|
DU4 DCT_EDI_ASSIGN_U4;
|
|
DU4 DCT_EDI_SHL_EQUAL_U4;
|
|
DU4 DCT_EDI_SHR_EQUAL_U4;
|
|
DU4 DCT_EDI_MUL_EQUAL_U4;
|
|
DU4 DCT_EDI_DIV_EQUAL_U4;
|
|
DU4 DCT_EDI_AND_EQUAL_U4;
|
|
DU4 DCT_EDI_OR_EQUAL_U4;
|
|
DU4 DCT_EDI_XOR_EQUAL_U4;
|
|
DU4 DCT_EDI_ADD_EQUAL_U4;
|
|
DU4 DCT_EDI_SUB_EQUAL_U4;
|
|
DU4 DCT_ADD64;
|
|
DU4 DCT_ADD32;
|
|
DU4 DCT_ADD8;
|
|
DU4 DCT_INC;
|
|
DU4 DCT_SUB64;
|
|
DU4 DCT_SUB32;
|
|
DU4 DCT_SUB8;
|
|
DU4 DCT_DEC;
|
|
DU4 DCT_ENTER;
|
|
DU4 DCT_LEAVE;
|
|
DU4 DCT_ENTER1;
|
|
DU4 DCT_LEAVE1;
|
|
DU4 DCT_ENTER2;
|
|
DU4 DCT_LEAVE2;
|
|
DU4 DCT_ADD_ESP32;
|
|
DU4 DCT_ADD_ESP8;
|
|
DU4 DCT_RET;
|
|
DU4 DCT_CALL;
|
|
DU4 DCT_CALL_INDIRECT;
|
|
DU4 DCT_CALL_INDIRECT2;
|
|
DU4 DCT_IRQ;
|
|
DU4 DCT_CLI;
|
|
DU4 DCT_STI;
|
|
DU4 DCT_GET_FLAGS;
|
|
DU4 DCT_SET_FLAGS;
|
|
DU4 DCT_GET_BASE_PTR;
|
|
DU4 DCT_SET_BASE_PTR;
|
|
DU4 DCT_GET_STACK_PTR;
|
|
DU4 DCT_SET_STACK_PTR;
|
|
DU4 DCT_GET_LABEL;
|
|
DU4 DCT_ABSOLUTE_ADDRESS;
|
|
DU4 DCT_LABEL;
|
|
DU4 DCT_TYPE;
|
|
DU4 DCT_BT;
|
|
DU4 DCT_BTS;
|
|
DU4 DCT_BTR;
|
|
DU4 DCT_BTC;
|
|
DU4 DCT_BSF;
|
|
DU4 DCT_BSR;
|
|
DU4 DCT_INSQUE;
|
|
DU4 DCT_INSQUE_REV;
|
|
DU4 DCT_REMQUE;
|
|
DU4 DCT_STRLEN;
|
|
DU4 DCT_MEMCPY;
|
|
DU4 DCT_MEMSET;
|
|
DU4 DCT_INPD;
|
|
DU4 DCT_INPW;
|
|
DU4 DCT_INP;
|
|
DU4 DCT_OUTPD;
|
|
DU4 DCT_OUTPW;
|
|
DU4 DCT_OUTP;
|
|
DU4 DCT_JMP;
|
|
DU4 DCT_SHORT_JMP;
|
|
DU4 DCT_SWITCH;
|
|
DU4 DCT_SKIPZ;
|
|
DU4 DCT_SKIPZ2;
|
|
DU4 DCT_SKIPNZ;
|
|
DU4 DCT_SKIPNZ2;
|
|
DU4 DCT_EQUAL_EQUAL_SKIPZ;
|
|
DU4 DCT_EQUAL_EQUAL_SKIPZ2;
|
|
DU4 DCT_NOT_EQUAL_TO_SKIPZ;
|
|
DU4 DCT_NOT_EQUAL_TO_SKIPZ2;
|
|
DU4 DCT_LESS_THAN_SKIPZ;
|
|
DU4 DCT_LESS_THAN_SKIPZ2;
|
|
DU4 DCT_GREATER_THAN_SKIPZ;
|
|
DU4 DCT_GREATER_THAN_SKIPZ2;
|
|
DU4 DCT_LESS_OR_EQUAL_SKIPZ;
|
|
DU4 DCT_LESS_OR_EQUAL_SKIPZ2;
|
|
DU4 DCT_GREATER_OR_EQUAL_SKIPZ;
|
|
DU4 DCT_GREATER_OR_EQUAL_SKIPZ2;
|
|
DU4 DCT_AND_AND_SKIPZ;
|
|
DU4 DCT_AND_AND_SKIPZ2;
|
|
DU4 DCT_AND_AND_SKIPNZ;
|
|
DU4 DCT_AND_AND_SKIPNZ2;
|
|
DU4 DCT_OR_OR_SKIPZ;
|
|
DU4 DCT_OR_OR_SKIPZ2;
|
|
DU4 DCT_OR_OR_SKIPNZ;
|
|
DU4 DCT_OR_OR_SKIPNZ2;
|
|
DU4 DCT_LEA_DISP32_ESI;
|
|
DU4 DCT_LEA_DISP8_ESI;
|
|
DU4 DCT_LEA_DISP32_EDI;
|
|
DU4 DCT_LEA_DISP8_EDI;
|
|
DU4 DCT_PUSH_U8;
|
|
DU4 DCT_PUSH_U4;
|
|
DU4 DCT_PUSH_U2;
|
|
DU4 DCT_PUSH_U1;
|
|
DU4 DCT_PUSH_NEG_U4;
|
|
DU4 DCT_PUSH_NEG_U2;
|
|
DU4 DCT_PUSH_NEG_U1;
|
|
DU4 DCT_PUSH_DOUBLE;
|
|
DU4 DCT_PUSH_U8_DISP32;
|
|
DU4 DCT_PUSH_U8_DISP8;
|
|
DU4 DCT_PUSH_ESI_U8_DISP32;
|
|
DU4 DCT_PUSH_ESI_U8_DISP8;
|
|
DU4 DCT_PUSH_EDI_U8_DISP32;
|
|
DU4 DCT_PUSH_EDI_U8_DISP8;
|
|
DU4 DCT_PUSH_DEREF_U8;
|
|
DU4 DCT_PUSH_U8_DISP32_SCALED;
|
|
DU4 DCT_BT_CONSTANT;
|
|
DU4 DCT_BTS_CONSTANT;
|
|
DU4 DCT_BTR_CONSTANT;
|
|
DU4 DCT_BTC_CONSTANT;
|
|
DU4 DCT_ESI_NEXT_EQUAL_U4;
|
|
DU4 DCT_EDI_NEXT_EQUAL_U4;
|
|
DU4 DCT_ADD_EQUAL_U8_CONSTANT_U1;
|
|
DU4 DCT_SUB_EQUAL_U8_CONSTANT_U1;
|
|
DU4 DCT_ADD_EQUAL_U4_CONSTANT_U1;
|
|
DU4 DCT_ESI_ADD_EQUAL_U4_CONSTANT_U1;
|
|
DU4 DCT_EDI_ADD_EQUAL_U4_CONSTANT_U1;
|
|
DU4 DCT_TABLE_END;
|
|
DCT_NULL:
|
|
DCT_NOP:
|
|
DCT_END_EXP:
|
|
DCT_ZERO:
|
|
DCT_U8:
|
|
DCT_U4:
|
|
DCT_U2:
|
|
DCT_U1:
|
|
DCT_DOUBLE:
|
|
DCT_STRING_CONSTANT:
|
|
DCT_EBP:
|
|
DCT_FS:
|
|
DCT_ESI:
|
|
DCT_EDI:
|
|
DCT_TO_DOUBLE:
|
|
DCT_TO_INT:
|
|
DCT_COM:
|
|
DCT_NOT:
|
|
DCT_UNARY_MINUS:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 4[EBP]
|
|
FCHS
|
|
FSTP U4 4[EBP]
|
|
POP EBP
|
|
POP EAX
|
|
POP EDX
|
|
DCT_ADDRESS:
|
|
DCT_U8_DISP32:
|
|
DCT_U4_DISP32:
|
|
DCT_U2_DISP32:
|
|
DCT_U1_DISP32:
|
|
DCT_U8_DISP8:
|
|
DCT_U4_DISP8:
|
|
DCT_U2_DISP8:
|
|
DCT_U1_DISP8:
|
|
DCT_FS_U8_DISP32:
|
|
DCT_FS_U4_DISP32:
|
|
DCT_FS_U2_DISP32:
|
|
DCT_FS_U1_DISP32:
|
|
DCT_ESI_U8_DISP32:
|
|
DCT_ESI_U4_DISP32:
|
|
DCT_ESI_U2_DISP32:
|
|
DCT_ESI_U1_DISP32:
|
|
DCT_ESI_U8_DISP8:
|
|
DCT_ESI_U4_DISP8:
|
|
DCT_ESI_U2_DISP8:
|
|
DCT_ESI_U1_DISP8:
|
|
DCT_EDI_U8_DISP32:
|
|
DCT_EDI_U4_DISP32:
|
|
DCT_EDI_U2_DISP32:
|
|
DCT_EDI_U1_DISP32:
|
|
DCT_EDI_U8_DISP8:
|
|
DCT_EDI_U4_DISP8:
|
|
DCT_EDI_U2_DISP8:
|
|
DCT_EDI_U1_DISP8:
|
|
DCT_DEREF_U8:
|
|
DCT_DEREF_U4:
|
|
DCT_DEREF_U2:
|
|
DCT_DEREF_U1:
|
|
DCT_ESI_DEREF_U8:
|
|
DCT_ESI_DEREF_U4:
|
|
DCT_ESI_DEREF_U2:
|
|
DCT_ESI_DEREF_U1:
|
|
DCT_EDI_DEREF_U8:
|
|
DCT_EDI_DEREF_U4:
|
|
DCT_EDI_DEREF_U2:
|
|
DCT_EDI_DEREF_U1:
|
|
DCT_U8_PP:
|
|
MOV EBX,EAX
|
|
MOV EDX,U4 4[EAX]
|
|
MOV EAX,U4 [EAX]
|
|
FLD U4 [EBX]
|
|
FLD1
|
|
FADDP
|
|
FSTP U4 [EBX]
|
|
DCT_U4_PP:
|
|
DCT_U2_PP:
|
|
DCT_U1_PP:
|
|
DCT_U8_MM:
|
|
MOV EBX,EAX
|
|
MOV EDX,U4 4[EAX]
|
|
MOV EAX,U4 [EAX]
|
|
FLD U4 [EBX]
|
|
FLD1
|
|
FSUBP
|
|
FSTP U4 [EBX]
|
|
DCT_U4_MM:
|
|
DCT_U2_MM:
|
|
DCT_U1_MM:
|
|
DCT_PP_U8:
|
|
FLD U4 [EAX]
|
|
FLD1
|
|
FADDP
|
|
FSTP U4 [EAX]
|
|
MOV EDX,U4 4[EAX]
|
|
MOV EAX,U4 [EAX]
|
|
DCT_PP_U4:
|
|
DCT_PP_U2:
|
|
DCT_PP_U1:
|
|
DCT_MM_U8:
|
|
FLD U4 [EAX]
|
|
FLD1
|
|
FSUBP
|
|
FSTP U4 [EAX]
|
|
MOV EDX,U4 4[EAX]
|
|
MOV EAX,U4 [EAX]
|
|
DCT_MM_U4:
|
|
DCT_MM_U2:
|
|
DCT_MM_U1:
|
|
DCT_ESI_U4_PP:
|
|
DCT_ESI_U4_MM:
|
|
DCT_ESI_PP_U4:
|
|
DCT_ESI_MM_U4:
|
|
DCT_EDI_U4_PP:
|
|
DCT_EDI_U4_MM:
|
|
DCT_EDI_PP_U4:
|
|
DCT_EDI_MM_U4:
|
|
DCT_LEA_DISP32_EBP:
|
|
DCT_LEA_DISP8_EBP:
|
|
DCT_U8_DISP32_SCALED:
|
|
DCT_U4_DISP32_SCALED:
|
|
DCT_U2_DISP32_SCALED:
|
|
DCT_SHL:
|
|
DCT_SHR:
|
|
DCT_SHL_CONSTANT1:
|
|
DCT_SHL_CONSTANT2:
|
|
DCT_SHR_CONSTANT1:
|
|
DCT_SHR_CONSTANT2:
|
|
DCT_POWER:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH 0
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FSTCW U4 4[EBP]
|
|
MOV AX,U2 4[EBP]
|
|
MOV U2 6[EBP],AX
|
|
OR AX,0x0C00
|
|
MOV U2 4[EBP],AX
|
|
FLDCW U4 4[EBP]
|
|
FLD U4 8[EBP]
|
|
FLD U4 16[EBP]
|
|
FYL2X // y*log2(x)
|
|
FST U4 16[EBP]
|
|
FRNDINT
|
|
FLD U4 16[EBP]
|
|
FSUBRP
|
|
F2XM1
|
|
FLD1
|
|
FADDP
|
|
FSTP U4 8[EBP]
|
|
FFREE
|
|
FINCSTP
|
|
FLD U4 16[EBP]
|
|
FLD U4 8[EBP]
|
|
FSCALE // ST0<<ST1
|
|
FSTP U4 16[EBP]
|
|
FFREE
|
|
FINCSTP
|
|
FLDCW U4 6[EBP]
|
|
POP EBP
|
|
ADD ESP,12
|
|
POP EAX
|
|
POP EDX
|
|
DCT_MULTIPLICATION:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 12[EBP]
|
|
FLD U4 4[EBP]
|
|
FMULP
|
|
FSTP U4 12[EBP]
|
|
POP EBP
|
|
ADD ESP,8
|
|
POP EAX
|
|
POP EDX
|
|
DCT_DIVISION:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 12[EBP]
|
|
FLD U4 4[EBP]
|
|
FDIVP
|
|
FSTP U4 12[EBP]
|
|
POP EBP
|
|
ADD ESP,8
|
|
POP EAX
|
|
POP EDX
|
|
DCT_REMAINDER:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 4[EBP]
|
|
FLD U4 12[EBP]
|
|
@@DMOD: FPREM
|
|
FSTSW
|
|
TEST AX,0x400
|
|
JNZ @@DMOD
|
|
FSTP U4 12[EBP]
|
|
FFREE
|
|
FINCSTP
|
|
POP EBP
|
|
ADD ESP,8
|
|
POP EAX
|
|
POP EDX
|
|
DCT_AND:
|
|
DCT_OR:
|
|
DCT_XOR:
|
|
DCT_ADDITION:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 12[EBP]
|
|
FLD U4 4[EBP]
|
|
FADDP
|
|
FSTP U4 12[EBP]
|
|
POP EBP
|
|
ADD ESP,8
|
|
POP EAX
|
|
POP EDX
|
|
DCT_SUBTRACTION:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 12[EBP]
|
|
FLD U4 4[EBP]
|
|
FSUBP
|
|
FSTP U4 12[EBP]
|
|
POP EBP
|
|
ADD ESP,8
|
|
POP EAX
|
|
POP EDX
|
|
DCT_EQUAL_EQUAL:
|
|
DCT_NOT_EQUAL_TO:
|
|
DCT_LESS_THAN:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 4[EBP]
|
|
FLD U4 12[EBP]
|
|
FCOMIP
|
|
MOV EAX,0
|
|
ADC EAX,0
|
|
XOR EDX,EDX
|
|
FFREE
|
|
FINCSTP
|
|
POP EBP
|
|
ADD ESP,16
|
|
DCT_GREATER_THAN:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 12[EBP]
|
|
FLD U4 4[EBP]
|
|
FCOMIP
|
|
MOV EAX,0
|
|
ADC EAX,0
|
|
XOR EDX,EDX
|
|
FFREE
|
|
FINCSTP
|
|
POP EBP
|
|
ADD ESP,16
|
|
DCT_LESS_OR_EQUAL:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 12[EBP]
|
|
FLD U4 4[EBP]
|
|
FCOMIP
|
|
MOV EAX,1
|
|
SBB EAX,0
|
|
XOR EDX,EDX
|
|
FFREE
|
|
FINCSTP
|
|
POP EBP
|
|
ADD ESP,16
|
|
DCT_GREATER_OR_EQUAL:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 4[EBP]
|
|
FLD U4 12[EBP]
|
|
FCOMIP
|
|
MOV EAX,1
|
|
SBB EAX,0
|
|
XOR EDX,EDX
|
|
FFREE
|
|
FINCSTP
|
|
POP EBP
|
|
ADD ESP,16
|
|
DCT_AND_AND:
|
|
DCT_OR_OR:
|
|
DCT_XOR_XOR:
|
|
DCT_COLON:
|
|
DCT_QUESTION:
|
|
DCT_ASSIGN_U8:
|
|
DCT_ASSIGN_U4:
|
|
DCT_ASSIGN_U2:
|
|
DCT_ASSIGN_U1:
|
|
DCT_SHL_EQUAL_U8:
|
|
DCT_SHL_EQUAL_U4:
|
|
DCT_SHL_EQUAL_U2:
|
|
DCT_SHL_EQUAL_U1:
|
|
DCT_SHR_EQUAL_U8:
|
|
DCT_SHR_EQUAL_U4:
|
|
DCT_SHR_EQUAL_U2:
|
|
DCT_SHR_EQUAL_U1:
|
|
DCT_MUL_EQUAL_U8:
|
|
POP EBX
|
|
ADD ESP,4
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 [EBX]
|
|
FLD U4 4[EBP]
|
|
FMULP
|
|
FST U4 [EBX]
|
|
FSTP U4 4[EBP]
|
|
POP EBP
|
|
POP EAX
|
|
POP EDX
|
|
DCT_MUL_EQUAL_U4:
|
|
DCT_MUL_EQUAL_U2:
|
|
DCT_MUL_EQUAL_U1:
|
|
DCT_DIV_EQUAL_U8:
|
|
POP EBX
|
|
ADD ESP,4
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 [EBX]
|
|
FLD U4 4[EBP]
|
|
FDIVP
|
|
FST U4 [EBX]
|
|
FSTP U4 4[EBP]
|
|
POP EBP
|
|
POP EAX
|
|
POP EDX
|
|
DCT_DIV_EQUAL_U4:
|
|
DCT_DIV_EQUAL_U2:
|
|
DCT_DIV_EQUAL_U1:
|
|
DCT_AND_EQUAL_U8:
|
|
DCT_AND_EQUAL_U4:
|
|
DCT_AND_EQUAL_U2:
|
|
DCT_AND_EQUAL_U1:
|
|
DCT_OR_EQUAL_U8:
|
|
DCT_OR_EQUAL_U4:
|
|
DCT_OR_EQUAL_U2:
|
|
DCT_OR_EQUAL_U1:
|
|
DCT_XOR_EQUAL_U8:
|
|
DCT_XOR_EQUAL_U4:
|
|
DCT_XOR_EQUAL_U2:
|
|
DCT_XOR_EQUAL_U1:
|
|
DCT_ADD_EQUAL_U8:
|
|
POP EBX
|
|
ADD ESP,4
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 [EBX]
|
|
FLD U4 4[EBP]
|
|
FADDP
|
|
FST U4 [EBX]
|
|
FSTP U4 4[EBP]
|
|
POP EBP
|
|
POP EAX
|
|
POP EDX
|
|
DCT_ADD_EQUAL_U4:
|
|
DCT_ADD_EQUAL_U2:
|
|
DCT_ADD_EQUAL_U1:
|
|
DCT_SUB_EQUAL_U8:
|
|
POP EBX
|
|
ADD ESP,4
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 [EBX]
|
|
FLD U4 4[EBP]
|
|
FSUBP
|
|
FST U4 [EBX]
|
|
FSTP U4 4[EBP]
|
|
POP EBP
|
|
POP EAX
|
|
POP EDX
|
|
DCT_SUB_EQUAL_U4:
|
|
DCT_SUB_EQUAL_U2:
|
|
DCT_SUB_EQUAL_U1:
|
|
DCT_ESI_ASSIGN_U4:
|
|
DCT_ESI_SHL_EQUAL_U4:
|
|
DCT_ESI_SHR_EQUAL_U4:
|
|
DCT_ESI_MUL_EQUAL_U4:
|
|
DCT_ESI_DIV_EQUAL_U4:
|
|
DCT_ESI_AND_EQUAL_U4:
|
|
DCT_ESI_OR_EQUAL_U4:
|
|
DCT_ESI_XOR_EQUAL_U4:
|
|
DCT_ESI_ADD_EQUAL_U4:
|
|
DCT_ESI_SUB_EQUAL_U4:
|
|
DCT_EDI_ASSIGN_U4:
|
|
DCT_EDI_SHL_EQUAL_U4:
|
|
DCT_EDI_SHR_EQUAL_U4:
|
|
DCT_EDI_MUL_EQUAL_U4:
|
|
DCT_EDI_DIV_EQUAL_U4:
|
|
DCT_EDI_AND_EQUAL_U4:
|
|
DCT_EDI_OR_EQUAL_U4:
|
|
DCT_EDI_XOR_EQUAL_U4:
|
|
DCT_EDI_ADD_EQUAL_U4:
|
|
DCT_EDI_SUB_EQUAL_U4:
|
|
DCT_ADD64:
|
|
DCT_ADD32:
|
|
DCT_ADD8:
|
|
DCT_INC:
|
|
DCT_SUB64:
|
|
DCT_SUB32:
|
|
DCT_SUB8:
|
|
DCT_DEC:
|
|
DCT_ENTER:
|
|
DCT_LEAVE:
|
|
DCT_ENTER1:
|
|
DCT_LEAVE1:
|
|
DCT_ENTER2:
|
|
DCT_LEAVE2:
|
|
DCT_ADD_ESP32:
|
|
DCT_ADD_ESP8:
|
|
DCT_RET:
|
|
DCT_CALL:
|
|
DCT_CALL_INDIRECT:
|
|
DCT_CALL_INDIRECT2:
|
|
DCT_IRQ:
|
|
DCT_CLI:
|
|
DCT_STI:
|
|
DCT_GET_FLAGS:
|
|
DCT_SET_FLAGS:
|
|
DCT_GET_BASE_PTR:
|
|
DCT_SET_BASE_PTR:
|
|
DCT_GET_STACK_PTR:
|
|
DCT_SET_STACK_PTR:
|
|
DCT_GET_LABEL:
|
|
DCT_ABSOLUTE_ADDRESS:
|
|
DCT_LABEL:
|
|
DCT_TYPE:
|
|
DCT_BT:
|
|
DCT_BTS:
|
|
DCT_BTR:
|
|
DCT_BTC:
|
|
DCT_BSF:
|
|
DCT_BSR:
|
|
DCT_INSQUE:
|
|
DCT_INSQUE_REV:
|
|
DCT_REMQUE:
|
|
DCT_STRLEN:
|
|
DCT_MEMCPY:
|
|
DCT_MEMSET:
|
|
DCT_INPD:
|
|
DCT_INPW:
|
|
DCT_INP:
|
|
DCT_OUTPD:
|
|
DCT_OUTPW:
|
|
DCT_OUTP:
|
|
DCT_JMP:
|
|
DCT_SHORT_JMP:
|
|
DCT_SWITCH:
|
|
DCT_SKIPZ:
|
|
DCT_SKIPZ2:
|
|
DCT_SKIPNZ:
|
|
DCT_SKIPNZ2:
|
|
DCT_EQUAL_EQUAL_SKIPZ:
|
|
DCT_EQUAL_EQUAL_SKIPZ2:
|
|
DCT_NOT_EQUAL_TO_SKIPZ:
|
|
DCT_NOT_EQUAL_TO_SKIPZ2:
|
|
DCT_LESS_THAN_SKIPZ:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 4[EBP]
|
|
FLD U4 12[EBP]
|
|
FCOMIP
|
|
MOV EAX,0
|
|
ADC EAX,0
|
|
FFREE
|
|
FINCSTP
|
|
POP EBP
|
|
ADD ESP,16
|
|
OR EAX,EAX
|
|
JZ DCT_LESS_THAN_SKIPZ
|
|
DCT_LESS_THAN_SKIPZ2:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 4[EBP]
|
|
FLD U4 12[EBP]
|
|
FCOMIP
|
|
MOV EAX,0
|
|
ADC EAX,0
|
|
FFREE
|
|
FINCSTP
|
|
POP EBP
|
|
ADD ESP,16
|
|
OR EAX,EAX
|
|
JZ U4 FAR_AWAY
|
|
DCT_GREATER_THAN_SKIPZ:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 12[EBP]
|
|
FLD U4 4[EBP]
|
|
FCOMIP
|
|
MOV EAX,0
|
|
ADC EAX,0
|
|
FFREE
|
|
FINCSTP
|
|
POP EBP
|
|
ADD ESP,16
|
|
OR EAX,EAX
|
|
JZ DCT_GREATER_THAN_SKIPZ
|
|
DCT_GREATER_THAN_SKIPZ2:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 12[EBP]
|
|
FLD U4 4[EBP]
|
|
FCOMIP
|
|
MOV EAX,0
|
|
ADC EAX,0
|
|
FFREE
|
|
FINCSTP
|
|
POP EBP
|
|
ADD ESP,16
|
|
OR EAX,EAX
|
|
JZ U4 FAR_AWAY
|
|
DCT_LESS_OR_EQUAL_SKIPZ:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 12[EBP]
|
|
FLD U4 4[EBP]
|
|
FCOMIP
|
|
MOV EAX,0
|
|
ADC EAX,0
|
|
FFREE
|
|
FINCSTP
|
|
POP EBP
|
|
ADD ESP,16
|
|
OR EAX,EAX
|
|
JNZ DCT_LESS_OR_EQUAL_SKIPZ
|
|
DCT_LESS_OR_EQUAL_SKIPZ2:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 12[EBP]
|
|
FLD U4 4[EBP]
|
|
FCOMIP
|
|
MOV EAX,0
|
|
ADC EAX,0
|
|
FFREE
|
|
FINCSTP
|
|
POP EBP
|
|
ADD ESP,16
|
|
OR EAX,EAX
|
|
JNZ U4 FAR_AWAY
|
|
DCT_GREATER_OR_EQUAL_SKIPZ:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 4[EBP]
|
|
FLD U4 12[EBP]
|
|
FCOMIP
|
|
MOV EAX,0
|
|
ADC EAX,0
|
|
FFREE
|
|
FINCSTP
|
|
POP EBP
|
|
ADD ESP,16
|
|
OR EAX,EAX
|
|
JNZ DCT_GREATER_OR_EQUAL_SKIPZ
|
|
DCT_GREATER_OR_EQUAL_SKIPZ2:
|
|
PUSH EDX
|
|
PUSH EAX
|
|
PUSH EBP
|
|
MOV EBP,ESP
|
|
FLD U4 4[EBP]
|
|
FLD U4 12[EBP]
|
|
FCOMIP
|
|
MOV EAX,0
|
|
ADC EAX,0
|
|
FFREE
|
|
FINCSTP
|
|
POP EBP
|
|
ADD ESP,16
|
|
OR EAX,EAX
|
|
JNZ U4 FAR_AWAY
|
|
DCT_AND_AND_SKIPZ:
|
|
DCT_AND_AND_SKIPZ2:
|
|
DCT_AND_AND_SKIPNZ:
|
|
DCT_AND_AND_SKIPNZ2:
|
|
DCT_OR_OR_SKIPZ:
|
|
DCT_OR_OR_SKIPZ2:
|
|
DCT_OR_OR_SKIPNZ:
|
|
DCT_OR_OR_SKIPNZ2:
|
|
DCT_LEA_DISP32_ESI:
|
|
DCT_LEA_DISP8_ESI:
|
|
DCT_LEA_DISP32_EDI:
|
|
DCT_LEA_DISP8_EDI:
|
|
DCT_PUSH_U8:
|
|
DCT_PUSH_U4:
|
|
DCT_PUSH_U2:
|
|
DCT_PUSH_U1:
|
|
DCT_PUSH_NEG_U4:
|
|
DCT_PUSH_NEG_U2:
|
|
DCT_PUSH_NEG_U1:
|
|
DCT_PUSH_DOUBLE:
|
|
DCT_PUSH_U8_DISP32:
|
|
DCT_PUSH_U8_DISP8:
|
|
DCT_PUSH_ESI_U8_DISP32:
|
|
DCT_PUSH_ESI_U8_DISP8:
|
|
DCT_PUSH_EDI_U8_DISP32:
|
|
DCT_PUSH_EDI_U8_DISP8:
|
|
DCT_PUSH_DEREF_U8:
|
|
DCT_PUSH_U8_DISP32_SCALED:
|
|
DCT_BT_CONSTANT:
|
|
DCT_BTS_CONSTANT:
|
|
DCT_BTR_CONSTANT:
|
|
DCT_BTC_CONSTANT:
|
|
DCT_ESI_NEXT_EQUAL_U4:
|
|
DCT_EDI_NEXT_EQUAL_U4:
|
|
DCT_ADD_EQUAL_U8_CONSTANT_U1:
|
|
DCT_SUB_EQUAL_U8_CONSTANT_U1:
|
|
DCT_ADD_EQUAL_U4_CONSTANT_U1:
|
|
DCT_ESI_ADD_EQUAL_U4_CONSTANT_U1:
|
|
DCT_EDI_ADD_EQUAL_U4_CONSTANT_U1:
|
|
DCT_TABLE_END:
|