622 lines
10 KiB
C++
622 lines
10 KiB
C++
asm {
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USE64
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// ************************************
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_D3_NORM::
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ENTER 0
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MOV RDX,U64 SF_ARG1[RBP]
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FLD U64 [RDX]
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FMUL ST0,ST0
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FLD U64 8[RDX]
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FMUL ST0,ST0
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FADDP ST1,ST0
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FLD U64 16[RDX]
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FMUL ST0,ST0
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FADDP ST1,ST0
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FSQRT
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FSTP U64 SF_ARG1[RBP]
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MOV RAX,U64 SF_ARG1[RBP]
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LEAVE
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RET1 8
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// ************************************
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_D3_SQR_NORM::
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ENTER 0
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MOV RDX,U64 SF_ARG1[RBP]
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FLD U64 [RDX]
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FMUL ST0,ST0
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FLD U64 8[RDX]
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FMUL ST0,ST0
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FADDP ST1,ST0
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FLD U64 16[RDX]
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FMUL ST0,ST0
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FADDP ST1,ST0
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FSTP U64 SF_ARG1[RBP]
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MOV RAX,U64 SF_ARG1[RBP]
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LEAVE
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RET1 8
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// ************************************
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_D3_DIST::
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ENTER 0
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MOV RDX,U64 SF_ARG1[RBP]
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MOV RBX,U64 SF_ARG2[RBP]
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FLD U64 [RDX]
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FSUB ST0,U64 [RBX]
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FMUL ST0,ST0
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FLD U64 8[RDX]
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FSUB ST0,U64 8[RBX]
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FMUL ST0,ST0
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FADDP ST1,ST0
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FLD U64 16[RDX]
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FSUB ST0,U64 16[RBX]
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FMUL ST0,ST0
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FADDP ST1,ST0
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FSQRT
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FSTP U64 SF_ARG1[RBP]
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MOV RAX,U64 SF_ARG1[RBP]
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LEAVE
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RET1 16
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// ************************************
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_D3_SQR_DIST::
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ENTER 0
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MOV RDX,U64 SF_ARG1[RBP]
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MOV RBX,U64 SF_ARG2[RBP]
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FLD U64 [RDX]
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FSUB ST0,U64 [RBX]
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FMUL ST0,ST0
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FLD U64 8[RDX]
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FSUB ST0,U64 8[RBX]
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FMUL ST0,ST0
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FADDP ST1,ST0
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FLD U64 16[RDX]
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FSUB ST0,U64 16[RBX]
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FMUL ST0,ST0
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FADDP ST1,ST0
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FSTP U64 SF_ARG1[RBP]
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MOV RAX,U64 SF_ARG1[RBP]
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LEAVE
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RET1 16
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// ************************************
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_D3_CROSS::
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ENTER 0
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MOV RDX,U64 SF_ARG1[RBP]
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MOV RBX,U64 SF_ARG2[RBP]
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MOV RAX,U64 SF_ARG3[RBP]
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FLD U64 8[RDX]
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FMUL ST0,U64 16[RBX]
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FLD U64 16[RDX]
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FMUL ST0,U64 8[RBX]
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FSUBP ST1,ST0
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FSTP U64 [RAX]
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FLD U64 [RDX]
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FMUL ST0,U64 16[RBX]
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FLD U64 16[RDX]
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FMUL ST0,U64 [RBX]
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FSUBRP ST1,ST0
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FSTP U64 8[RAX]
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FLD U64 [RDX]
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FMUL ST0,U64 8[RBX]
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FLD U64 8[RDX]
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FMUL ST0,U64 [RBX]
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FSUBP ST1,ST0
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FSTP U64 16[RAX]
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LEAVE
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RET1 24
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// ************************************
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_D3_DOT::
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ENTER 0
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MOV RDX,U64 SF_ARG1[RBP]
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MOV RBX,U64 SF_ARG2[RBP]
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FLD U64 [RDX]
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FMUL ST0,U64 [RBX]
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FLD U64 8[RDX]
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FMUL ST0,U64 8[RBX]
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FADDP ST1,ST0
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FLD U64 16[RDX]
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FMUL ST0,U64 16[RBX]
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FADDP ST1,ST0
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FSTP U64 SF_ARG1[RBP]
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MOV RAX,U64 SF_ARG1[RBP]
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LEAVE
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RET1 16
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// ************************************
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_D3_ADD::
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ENTER 0
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MOV RDX,U64 SF_ARG1[RBP]
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MOV RBX,U64 SF_ARG2[RBP]
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MOV RAX,U64 SF_ARG3[RBP]
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FLD U64 [RDX]
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FADD ST0,U64 [RBX]
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FSTP U64 [RAX]
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FLD U64 8[RDX]
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FADD ST0,U64 8[RBX]
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FSTP U64 8[RAX]
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FLD U64 16[RDX]
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FADD ST0,U64 16[RBX]
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FSTP U64 16[RAX]
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LEAVE
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RET1 24
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// ************************************
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_D3_SUB::
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ENTER 0
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MOV RDX,U64 SF_ARG1[RBP]
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MOV RBX,U64 SF_ARG2[RBP]
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MOV RAX,U64 SF_ARG3[RBP]
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FLD U64 [RDX]
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FSUB ST0,U64 [RBX]
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FSTP U64 [RAX]
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FLD U64 8[RDX]
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FSUB ST0,U64 8[RBX]
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FSTP U64 8[RAX]
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FLD U64 16[RDX]
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FSUB ST0,U64 16[RBX]
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FSTP U64 16[RAX]
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LEAVE
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RET1 24
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// ************************************
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_D3_MUL::
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ENTER 0
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MOV RBX,U64 SF_ARG2[RBP]
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MOV RAX,U64 SF_ARG3[RBP]
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FLD U64 SF_ARG1[RBP]
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FLD ST0
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FMUL ST0,U64 [RBX]
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FSTP U64 [RAX]
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FLD ST0
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FMUL ST0,U64 8[RBX]
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FSTP U64 8[RAX]
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FMUL ST0,U64 16[RBX]
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FSTP U64 16[RAX]
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LEAVE
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RET1 24
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// ************************************
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_D3_DIV::
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ENTER 0
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MOV RBX,U64 SF_ARG2[RBP]
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MOV RAX,U64 SF_ARG3[RBP]
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FLD U64 SF_ARG1[RBP]
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FLD ST0
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FDIVR ST0,U64 [RBX]
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FSTP U64 [RAX]
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FLD ST0
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FDIVR ST0,U64 8[RBX]
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FSTP U64 8[RAX]
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FDIVR ST0,U64 16[RBX]
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FSTP U64 16[RAX]
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LEAVE
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RET1 24
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// ************************************
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_D3_ZERO::
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ENTER 0
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MOV RAX,U64 SF_ARG1[RBP]
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XOR RDX,RDX
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MOV U64 [RAX],RDX
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MOV U64 8[RAX],RDX
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MOV U64 16[RAX],RDX
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LEAVE
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RET1 8
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// ************************************
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_D3_COPY::
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ENTER 0
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MOV RAX,U64 SF_ARG1[RBP]
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MOV RBX,U64 SF_ARG2[RBP]
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MOV RDX,U64 [RBX]
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MOV U64 [RAX],RDX
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MOV RDX,U64 8[RBX]
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MOV U64 8[RAX],RDX
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MOV RDX,U64 16[RBX]
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MOV U64 16[RAX],RDX
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LEAVE
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RET1 16
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// ************************************
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_D3_EQU::
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ENTER 0
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MOV RAX,U64 SF_ARG1[RBP]
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MOV RDX,U64 SF_ARG2[RBP]
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MOV U64 [RAX],RDX
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MOV RDX,U64 SF_ARG3[RBP]
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MOV U64 8[RAX],RDX
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MOV RDX,U64 SF_ARG4[RBP]
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MOV U64 16[RAX],RDX
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LEAVE
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RET1 32
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// ************************************
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_D3_ADD_EQU::
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ENTER 0
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MOV RAX,U64 SF_ARG1[RBP]
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MOV RBX,U64 SF_ARG2[RBP]
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FLD U64 [RAX]
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FADD ST0,U64 [RBX]
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FSTP U64 [RAX]
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FLD U64 8[RAX]
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FADD ST0,U64 8[RBX]
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FSTP U64 8[RAX]
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FLD U64 16[RAX]
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FADD ST0,U64 16[RBX]
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FSTP U64 16[RAX]
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LEAVE
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RET1 16
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// ************************************
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_D3_SUB_EQU::
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ENTER 0
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MOV RAX,U64 SF_ARG1[RBP]
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MOV RBX,U64 SF_ARG2[RBP]
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FLD U64 [RAX]
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FSUB ST0,U64 [RBX]
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FSTP U64 [RAX]
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FLD U64 8[RAX]
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FSUB ST0,U64 8[RBX]
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FSTP U64 8[RAX]
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FLD U64 16[RAX]
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FSUB ST0,U64 16[RBX]
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FSTP U64 16[RAX]
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LEAVE
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RET1 16
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// ************************************
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_D3_MUL_EQU::
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ENTER 0
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MOV RAX,U64 SF_ARG1[RBP]
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FLD U64 SF_ARG2[RBP]
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FLD ST0
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FMUL ST0,U64 [RAX]
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FSTP U64 [RAX]
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FLD ST0
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FMUL ST0,U64 8[RAX]
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FSTP U64 8[RAX]
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FMUL ST0,U64 16[RAX]
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FSTP U64 16[RAX]
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LEAVE
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RET1 16
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// ************************************
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_D3_DIV_EQU::
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ENTER 0
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MOV RAX,U64 SF_ARG1[RBP]
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FLD U64 SF_ARG2[RBP]
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FLD ST0
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FDIVR ST0,U64 [RAX]
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FSTP U64 [RAX]
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FLD ST0
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FDIVR ST0,U64 8[RAX]
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FSTP U64 8[RAX]
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FDIVR ST0,U64 16[RAX]
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FSTP U64 16[RAX]
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LEAVE
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RET1 16
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// ************************************
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_D3_UNIT::
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ENTER 0
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MOV RDX,U64 SF_ARG1[RBP]
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FLD U64 [RDX]
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FMUL ST0,ST0
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FLD U64 8[RDX]
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FMUL ST0,ST0
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FADDP ST1,ST0
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FLD U64 16[RDX]
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FMUL ST0,ST0
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FADDP ST1,ST0
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FSQRT
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FST U64 SF_ARG1[RBP]
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MOV RBX,SF_ARG1[RBP]
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OR RBX,RBX
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JZ @@05
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FLD ST0
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FDIVR ST0,U64 [RAX]
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FSTP U64 [RAX]
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FLD ST0
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FDIVR ST0,U64 8[RAX]
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FSTP U64 8[RAX]
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FDIVR ST0,U64 16[RAX]
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FSTP U64 16[RAX]
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LEAVE
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RET1 8
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@@05: FFREE ST0
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FINCSTP
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LEAVE
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RET1 8
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// ************************************
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_SQR::
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ENTER 0
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FLD U64 SF_ARG1[RBP]
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FMUL ST0,ST0
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FSTP U64 SF_ARG1[RBP]
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MOV RAX,U64 SF_ARG1[RBP]
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LEAVE
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RET1 8
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// ************************************
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_SIGN::
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ENTER 0
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FLD U64 SF_ARG1[RBP]
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FTST
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FSTSW
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FFREE ST0
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FINCSTP
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MOV RDX,RAX
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XOR RAX,RAX
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BT RDX,14
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JC @@05
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MOV RAX,1.0
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BT RDX,8
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JNC @@05
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MOV RAX,-1.0
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@@05: LEAVE
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RET1 8
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// ************************************
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_ARG::
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ENTER 0
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FLD U64 SF_ARG2[RBP]
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FLD U64 SF_ARG1[RBP]
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@@05: FPATAN
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FSTSW
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TEST AX,0x400
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JNZ @@05
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FSTP U64 SF_ARG1[RBP]
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MOV RAX,U64 SF_ARG1[RBP]
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LEAVE
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RET1 16
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// ************************************
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_ROUND::
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ENTER 8
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FSTCW U16 -8[RBP]
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MOV AX,U16 -8[RBP]
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MOV U16 -6[RBP],AX
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AND AX,~0x0C00
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MOV U16 -8[RBP],AX
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FLDCW U16 -8[RBP]
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FLD U64 SF_ARG1[RBP]
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FRNDINT
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FSTP U64 SF_ARG1[RBP]
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MOV RAX,U64 SF_ARG1[RBP]
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FLDCW U16 -6[RBP]
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LEAVE
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RET1 8
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// ************************************
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_TRUNC::
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ENTER 8
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FSTCW U16 -8[RBP]
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MOV AX,U16 -8[RBP]
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MOV U16 -6[RBP],AX
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OR AX,0x0C00
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MOV U16 -8[RBP],AX
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FLDCW U16 -8[RBP]
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FLD U64 SF_ARG1[RBP]
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FRNDINT
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FSTP U64 SF_ARG1[RBP]
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MOV RAX,U64 SF_ARG1[RBP]
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FLDCW U16 -6[RBP]
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LEAVE
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RET1 8
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// ************************************
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_FLOOR::
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ENTER 8
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FSTCW U16 -8[RBP]
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MOV AX,U16 -8[RBP]
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MOV U16 -6[RBP],AX
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AND AX,~0x0C00
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OR AX,0x0400
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MOV U16 -8[RBP],AX
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FLDCW U16 -8[RBP]
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FLD U64 SF_ARG1[RBP]
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FRNDINT
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FSTP U64 SF_ARG1[RBP]
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MOV RAX,U64 SF_ARG1[RBP]
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FLDCW U16 -6[RBP]
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LEAVE
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RET1 8
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// ************************************
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_CEIL::
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ENTER 8
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FSTCW U16 -8[RBP]
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MOV AX,U16 -8[RBP]
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MOV U16 -6[RBP],AX
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AND AX,~0x0C00
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OR AX,0x0800
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MOV U16 -8[RBP],AX
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FLDCW U16 -8[RBP]
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FLD U64 SF_ARG1[RBP]
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FRNDINT
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FSTP U64 SF_ARG1[RBP]
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MOV RAX,SF_ARG1[RBP]
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FLDCW U16 -6[RBP]
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LEAVE
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RET1 8
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// ************************************
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SYS_POW::
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// RAX=RDX`RAX
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ENTER 24
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OR RAX,RAX //To power of zero?
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JNZ @@05
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MOV RAX,1.0
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JMP @@20
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@@05: OR RDX,RDX //zero to a power?
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JNZ @@10
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XOR RAX,RAX
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JMP @@20
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@@10: MOV RCX,RAX //RCX=pow
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MOV U64 -8[RBP],RDX
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MOV U64 -16[RBP],RAX
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FSTCW U16 -24[RBP]
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MOV AX,U16 -24[RBP]
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MOV U16 -22[RBP],AX
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OR AX,0x0C00
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MOV U16 -24[RBP],AX
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FLDCW U16 -24[RBP]
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FLD U64 -16[RBP]
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FLD U64 -8[RBP]
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FABS //base should be pos
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FYL2X // y*log2(x)
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FST U64 -8[RBP]
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FRNDINT
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FLD U64 -8[RBP]
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FSUBRP ST1,ST0
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F2XM1
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FLD1
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FADDP ST1,ST0
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FSTP U64 -16[RBP]
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FLD U64 -8[RBP]
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FLD U64 -16[RBP]
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FSCALE // ST0<<ST1
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OR RDX,RDX //was base neg?
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JGE @@15
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MOV U64 -16[RBP],RCX
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FLD U64 -16[RBP]
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FISTTP U64 -16[RBP]
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TEST U64 -16[RBP],1
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JZ @@15 //was pow odd?
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FCHS
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@@15: FSTP U64 -8[RBP]
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FFREE ST0
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FINCSTP
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FLDCW U16 -22[RBP]
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MOV RAX,U64 -8[RBP]
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@@20: LEAVE
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RET
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// ************************************
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_POW::
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ENTER 0
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MOV RAX,U64 SF_ARG2[RBP]
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MOV RDX,U64 SF_ARG1[RBP]
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CALL SYS_POW
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LEAVE
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RET1 16
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// ************************************
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_POW10::
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ENTER 16
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FSTCW U16 -8[RBP]
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MOV AX,U16 -8[RBP]
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MOV U16 -6[RBP],AX
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OR AX,0x0C00
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MOV U16 -8[RBP],AX
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FLDCW U16 -8[RBP]
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FLDL2T
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FLD U64 SF_ARG1[RBP]
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FMULP ST1,ST0
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FST U64 SF_ARG1[RBP]
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FRNDINT
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FLD U64 SF_ARG1[RBP]
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FSUBRP ST1,ST0
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F2XM1
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FLD1
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FADDP ST1,ST0
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FSTP U64 -16[RBP]
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FLD U64 SF_ARG1[RBP]
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FLD U64 -16[RBP]
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FSCALE // ST0<<ST1
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FSTP U64 -16[RBP]
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FFREE ST0
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FINCSTP
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FLDCW U16 -6[RBP]
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MOV RAX,U64 -16[RBP]
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LEAVE
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RET1 8
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// ************************************
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_EXP::
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ENTER 16
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FSTCW U16 -8[RBP]
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MOV AX,U16 -8[RBP]
|
|
MOV U16 -6[RBP],AX
|
|
OR AX,0x0C00
|
|
MOV U16 -8[RBP],AX
|
|
FLDCW U16 -8[RBP]
|
|
|
|
FLDL2E
|
|
FLD U64 SF_ARG1[RBP]
|
|
FMULP ST1,ST0
|
|
FST U64 SF_ARG1[RBP]
|
|
FRNDINT
|
|
FLD U64 SF_ARG1[RBP]
|
|
FSUBRP ST1,ST0
|
|
F2XM1
|
|
FLD1
|
|
FADDP ST1,ST0
|
|
FSTP U64 -16[RBP]
|
|
FLD U64 SF_ARG1[RBP]
|
|
FLD U64 -16[RBP]
|
|
FSCALE // ST0<<ST1
|
|
FSTP U64 -16[RBP]
|
|
FFREE ST0
|
|
FINCSTP
|
|
|
|
FLDCW U16 -6[RBP]
|
|
MOV RAX,U64 -16[RBP]
|
|
LEAVE
|
|
RET1 8
|
|
// ************************************
|
|
_LOG10::
|
|
ENTER 8
|
|
FLDLG2
|
|
FLD U64 SF_ARG1[RBP]
|
|
FYL2X // y*log2(x)
|
|
FSTP U64 -8[RBP]
|
|
MOV RAX,U64 -8[RBP]
|
|
LEAVE
|
|
RET1 8
|
|
// ************************************
|
|
_LOG2::
|
|
ENTER 8
|
|
FLD1
|
|
FLD U64 SF_ARG1[RBP]
|
|
FYL2X // y*log2(x)
|
|
FSTP U64 -8[RBP]
|
|
MOV RAX,U64 -8[RBP]
|
|
LEAVE
|
|
RET1 8
|
|
// ************************************
|
|
_LN::
|
|
ENTER 8
|
|
FLDLN2
|
|
FLD U64 SF_ARG1[RBP]
|
|
FYL2X // y*log2(x)
|
|
FSTP U64 -8[RBP]
|
|
MOV RAX,U64 -8[RBP]
|
|
LEAVE
|
|
RET1 8
|
|
// ************************************
|
|
_FLDCW::
|
|
ENTER 0
|
|
FLDCW U16 SF_ARG1[RBP]
|
|
LEAVE
|
|
RET1 8
|
|
// ************************************
|
|
_FSTCW::
|
|
ENTER 8
|
|
FSTCW U16 -8[RBP]
|
|
MOVZX RAX,U16 -8[RBP]
|
|
LEAVE
|
|
RET
|
|
// ************************************
|
|
_FSTSW::
|
|
XOR RAX,RAX
|
|
FSTSW
|
|
RET
|
|
// ************************************
|
|
_FCLEX::
|
|
FCLEX
|
|
RET
|
|
// ************************************
|
|
_FXSAVE::
|
|
ENTER 0
|
|
MOV RAX,U64 SF_ARG1[RBP]
|
|
FXSAVE U64 [RAX]
|
|
LEAVE
|
|
RET1 8
|
|
// ************************************
|
|
_FXRSTOR::
|
|
ENTER 0
|
|
MOV RAX,U64 SF_ARG1[RBP]
|
|
FXRSTOR U64 [RAX]
|
|
LEAVE
|
|
RET1 8
|
|
}
|